taoyilee / clacc
Deep Learning Accelerator (Convolution Neural Networks)
☆179Updated 7 years ago
Alternatives and similar repositories for clacc:
Users that are interested in clacc are comparing it to the libraries listed below
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆157Updated 5 years ago
- ☆108Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆100Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆196Updated 2 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆150Updated 5 years ago
- IC implementation of Systolic Array for TPU☆232Updated 6 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆66Updated 2 months ago
- FPGA/AES/LeNet/VGG16☆103Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆171Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆177Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆99Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- IC implementation of TPU☆122Updated 5 years ago
- ☆64Updated 6 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆190Updated 4 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- An LeNet RTL implement onto FPGA☆46Updated 7 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆149Updated 10 months ago
- ☆38Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆36Updated 2 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆72Updated last year
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 7 years ago
- verilog实现systolic array及配套IO☆8Updated 5 months ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- Convolutional Neural Network RTL-level Design☆51Updated 3 years ago
- Vitis HLS Library for FINN☆192Updated last week
- ☆12Updated 5 years ago