taoyilee / claccView external linksLinks
Deep Learning Accelerator (Convolution Neural Networks)
☆197Dec 15, 2017Updated 8 years ago
Alternatives and similar repositories for clacc
Users that are interested in clacc are comparing it to the libraries listed below
Sorting:
- ☆124Jul 22, 2020Updated 5 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆217Dec 22, 2020Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆180Dec 14, 2019Updated 6 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆242Apr 10, 2023Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆194Mar 20, 2024Updated last year
- Hardware accelerator for convolutional neural networks☆65Aug 9, 2022Updated 3 years ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆233Aug 24, 2020Updated 5 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆438Dec 2, 2019Updated 6 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated last month
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆383Dec 27, 2023Updated 2 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- Berkeley's Spatial Array Generator☆1,215Feb 7, 2026Updated last week
- ☆377May 11, 2023Updated 2 years ago
- This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…☆2,047Nov 8, 2025Updated 3 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆47Oct 14, 2022Updated 3 years ago
- ☆653Jan 13, 2021Updated 5 years ago
- eyeriss-chisel3☆40May 2, 2022Updated 3 years ago
- ☆13Aug 21, 2019Updated 6 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- IC implementation of Systolic Array for TPU☆330Oct 21, 2024Updated last year
- ☆35Mar 1, 2019Updated 6 years ago
- 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用☆580Jun 18, 2018Updated 7 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Nov 1, 2025Updated 3 months ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- RTL, Cmodel, and testbench for NVDLA☆2,023Mar 2, 2022Updated 3 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 3 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆142Mar 30, 2018Updated 7 years ago
- ☆19Dec 3, 2019Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆181Jun 20, 2024Updated last year
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆32Sep 22, 2018Updated 7 years ago
- RTL implementation of Flex-DPE.☆115Feb 22, 2020Updated 5 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year