williamyang4978 / PipeCNN_WinogradLinks
An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
☆37Updated 4 years ago
Alternatives and similar repositories for PipeCNN_Winograd
Users that are interested in PipeCNN_Winograd are comparing it to the libraries listed below
Sorting:
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆66Updated 6 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆36Updated 6 years ago
- A collection of tutorials for the fpgaConvNet framework.☆43Updated 10 months ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago
- ☆71Updated 5 years ago
- ☆47Updated 7 years ago
- 中文:☆101Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- ☆65Updated 6 years ago
- Codes to implement MobileNet V2 in a FPGA☆27Updated 4 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- ☆34Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago