williamyang4978 / PipeCNN_WinogradLinks
An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
☆39Updated 4 years ago
Alternatives and similar repositories for PipeCNN_Winograd
Users that are interested in PipeCNN_Winograd are comparing it to the libraries listed below
Sorting:
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 10 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- ☆35Updated 6 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆27Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- ☆71Updated 6 years ago
- 基于HLS的高效深度卷积神经网络FPGA实 现方法☆71Updated 6 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- ☆48Updated 7 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆46Updated last year
- ☆11Updated last year
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- ☆71Updated 5 years ago
- Codes to implement MobileNet V2 in a FPGA☆28Updated 4 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33Updated 6 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- ☆46Updated 5 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆103Updated 9 months ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago