mediaic / MSoC-HLSLinks
Multimedia SoC Design with Specialization on Application Acceleration with High-Level-Synthesis [2020 Fall]
☆12Updated 4 years ago
Alternatives and similar repositories for MSoC-HLS
Users that are interested in MSoC-HLS are comparing it to the libraries listed below
Sorting:
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Updated 6 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated 11 months ago
- ☆16Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆28Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆13Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- ☆30Updated 6 years ago
- ☆29Updated 8 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 3 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- ☆36Updated 6 months ago
- ☆72Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- CNN accelerator☆27Updated 8 years ago
- course design☆22Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆61Updated last year
- ☆63Updated 5 months ago
- ☆17Updated 4 years ago
- ☆71Updated 5 years ago
- ☆15Updated 2 years ago