mediaic / MSoC-HLS
Multimedia SoC Design with Specialization on Application Acceleration with High-Level-Synthesis [2020 Fall]
☆11Updated 3 years ago
Related projects: ⓘ
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- ☆21Updated 4 years ago
- CNN accelerator☆26Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆20Updated 5 years ago
- course design☆19Updated 6 years ago
- ☆3Updated 3 years ago
- HLS for Networks-on-Chip☆27Updated 3 years ago
- first-order deep learning accelerator model☆18Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆23Updated 4 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆11Updated 7 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆52Updated last year
- A DSL for Systolic Arrays☆73Updated 5 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆33Updated 3 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆45Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 3 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 7 years ago
- SystemC training aimed at TLM.☆24Updated 4 years ago
- Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.☆23Updated 10 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- Template for project1 TPU☆11Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆62Updated last month
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆57Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆35Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆29Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆41Updated 3 years ago