Alternatives and similar repositories for CNNAF-CNN-Accelerator_init:

Users that are interested in CNNAF-CNN-Accelerator_init are comparing it to the libraries listed below

• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆26Updated 5 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆15Updated 3 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆21Updated 3 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆100Updated 4 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆26Updated 4 years ago
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆40Updated 6 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 3 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆30Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆41Updated 5 months ago
• zhongguanggong / ggz
  使用FPGA实现CNN模型
  ☆13Updated 5 years ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆17Updated 3 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆36Updated 2 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆139Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 6 years ago
• bird1and1fish / Frame_Difference
  FPGA实现动态图像识别
  ☆16Updated 4 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆63Updated last month
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆28Updated last year
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆48Updated 6 years ago
• ZhaoqxCN / PYNQ-CNN-ATTEMPT
  Some attempts to build CNN on PYNQ.
  ☆24Updated 5 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆93Updated 6 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆77Updated 3 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆84Updated 4 years ago
• FloyedShen / mnist_hls
  Lenet for MNIST handwritten digit recognition using Vivado hls tool
  ☆36Updated 4 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆37Updated 5 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆22Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆20Updated 3 years ago
• ignperez-udec / MobileNet-V2-inference-HLS
  Codes to implement MobileNet V2 in a FPGA
  ☆24Updated 4 years ago