Alternatives and similar repositories for CNNAF-CNN-Accelerator_init

Users that are interested in CNNAF-CNN-Accelerator_init are comparing it to the libraries listed below

• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 4 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆37Updated last year
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆47Updated 2 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆113Updated 5 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆21Updated 4 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆66Updated 6 months ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 5 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• Mattjesc / Efficient-FPGA-CNN-Accelerator
  Efficient FPGA-Based Accelerator for Convolutional Neural Networks
  ☆21Updated last year
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆34Updated 3 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆34Updated 6 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆34Updated 5 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆104Updated 6 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆17Updated 3 years ago
• zhongguanggong / ggz
  使用FPGA实现CNN模型
  ☆15Updated 6 years ago
• louislxw / pe_array
  A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…
  ☆11Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆164Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆93Updated 2 weeks ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆220Updated 2 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆185Updated last year
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆17Updated 2 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆12Updated 4 years ago
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆49Updated 7 years ago
• Ziheng-W / systolic-array-verilog
  verilog实现systolic array及配套IO
  ☆9Updated 8 months ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆24Updated 3 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆53Updated 7 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆128Updated 2 months ago