Hossamomar / EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-DesignLinks
Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional n…
☆16Updated 6 years ago
Alternatives and similar repositories for EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design
Users that are interested in EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design are comparing it to the libraries listed below
Sorting:
- This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.☆14Updated 7 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆23Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- System Verilog code describing a fully combinational binarized neural network.☆34Updated 6 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- ☆66Updated 3 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆110Updated 5 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆63Updated 8 years ago
- Microshift Compression: An Efficient Image Compression Algorithm for Hardware☆32Updated 4 years ago
- Digital Design Lab Spring 2019 Final Project☆11Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated last year
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- ☆65Updated 6 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆34Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆35Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆55Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago