Alternatives and similar repositories for EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design

Users that are interested in EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design are comparing it to the libraries listed below

• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆112Updated 5 years ago
• EEESlab / combinational-bnn
  System Verilog code describing a fully combinational binarized neural network.
  ☆34Updated 7 years ago
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆41Updated this week
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆163Updated 8 years ago
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆111Updated 6 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆20Updated 7 years ago
• mtmd / FPGA_Based_CNN
  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
  ☆185Updated 8 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 5 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆66Updated 8 years ago
• Xilinx / LSTM-PYNQ
  ☆90Updated 5 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆52Updated 8 years ago
• Johnny-Zou / FPGA-Mnist
  Hand written number classification done in hardware (De1-SoC board) using neural networks
  ☆24Updated 7 years ago
• chenhaoc / cnnhwpe
  ☆65Updated 3 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• diaoenmao / FPGA-CNN
  FPGA implementation of Cellular Neural Network (CNN)
  ☆142Updated 7 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆31Updated 9 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆48Updated 5 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• shaneleonard / neural-hardware
  Verilog library for implementing neural networks.
  ☆26Updated 11 years ago
• cornell-zhang / facedetect-fpga
  ☆46Updated 5 years ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆279Updated 5 years ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆176Updated 6 years ago
• JunnanShan / AlexNet-FPGA-implementation
  This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.
  ☆21Updated 7 years ago
• suhasr1991 / Convolutional-Neural-Network-hardware-using-Verilog
  A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…
  ☆18Updated 7 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆68Updated 5 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆30Updated 2 years ago