Hossamomar / EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-DesignView on GitHub
Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional n…
☆16Jul 4, 2018Updated 7 years ago
Alternatives and similar repositories for EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design
Users that are interested in EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Dec 19, 2018Updated 7 years ago
- Convolutional Neural Network (CNN) image classification of handwritten digits in Xilinx FPGA☆14Sep 12, 2019Updated 6 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- This is a learning tool for junior/senior level electrical engineering students to get a better understanding of OFDM communication throu…☆18Feb 18, 2025Updated last year
- Senior Design☆12Jan 26, 2025Updated last year
- A DNN Accelerator implemented with RTL.☆70Jan 9, 2025Updated last year
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 7 years ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 4 years ago
- ☆33Jul 28, 2020Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆22Jan 9, 2024Updated 2 years ago
- Brilliantly Radical Artificially Intelligent Neural Machine☆18Dec 28, 2017Updated 8 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- 64 bit fasm tutorials.☆13Oct 13, 2015Updated 10 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- CK workflow, portable packages and other artifacts for the ReQuEST-ASPLOS'18 submission:☆12Jan 16, 2019Updated 7 years ago
- Accelerate convolution neural network for face recognition using GPU☆15Nov 24, 2020Updated 5 years ago
- The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))☆11Sep 27, 2019Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆117Feb 22, 2021Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆39Nov 25, 2019Updated 6 years ago
- ☆11Nov 22, 2022Updated 3 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆21May 4, 2023Updated 3 years ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 8 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆116Jun 24, 2017Updated 9 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆19Jul 19, 2024Updated last year
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 6 years ago
- Curtis VCO schematics & PCB layout☆15May 28, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK☆16Dec 2, 2018Updated 7 years ago
- ☆99Jan 22, 2026Updated 5 months ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 9 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆24Aug 28, 2024Updated last year
- A HARDWARE IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS FOR INFERENCE☆35Mar 10, 2020Updated 6 years ago
- Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"☆27Dec 9, 2018Updated 7 years ago
- FPGA and GPU acceleration of LeNet5☆36Jul 9, 2019Updated 6 years ago