This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
☆787Dec 10, 2019Updated 6 years ago
Alternatives and similar repositories for Accelerating-CNN-with-FPGA
Users that are interested in Accelerating-CNN-with-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,373Feb 14, 2022Updated 4 years ago
- Python on Zynq FPGA for Convolutional Neural Networks☆624May 15, 2018Updated 7 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆909Jul 29, 2024Updated last year
- 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用☆588Jun 18, 2018Updated 7 years ago
- FPGA Accelerator for CNN using Vivado HLS☆339Oct 25, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- CNN acceleration on virtex-7 FPGA with verilog HDL☆480Feb 27, 2018Updated 8 years ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆370May 2, 2023Updated 2 years ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆773May 26, 2017Updated 8 years ago
- 中文版 Parallel Programming for FPGAs☆763Aug 21, 2024Updated last year
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆116Jun 24, 2017Updated 8 years ago
- OpenCL Labs for PAPAA Summer School 2016 Edition☆46Jul 24, 2017Updated 8 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆586Feb 19, 2021Updated 5 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆338Jul 9, 2019Updated 6 years ago
- Accelerate convolution neural network for face recognition using GPU☆13Nov 24, 2020Updated 5 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆257Dec 29, 2018Updated 7 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Jun 11, 2019Updated 6 years ago
- 中文：☆109Nov 29, 2019Updated 6 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆273May 6, 2023Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆196Mar 20, 2024Updated 2 years ago
- FPGA☆160Jun 29, 2024Updated last year
- Implement Tiny YOLO v3 on ZYNQ☆312Apr 14, 2025Updated 11 months ago
- 一个开源的FPGA神经网络加速器。☆193Sep 4, 2023Updated 2 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆214Aug 23, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆157Jan 23, 2020Updated 6 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Apr 12, 2021Updated 5 years ago
- Verilog Generator of Neural Net Digit Detector for FPGA☆313Sep 7, 2022Updated 3 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆114Feb 22, 2021Updated 5 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆303Aug 16, 2018Updated 7 years ago
- hls code zynq 7020 pynq z2 CNN☆91Mar 15, 2019Updated 7 years ago
- An open source library for image processing on FPGA.☆629Jun 16, 2015Updated 10 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆285Dec 5, 2019Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93May 25, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆448Dec 2, 2019Updated 6 years ago
- ☆32Apr 21, 2019Updated 6 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆142Mar 30, 2018Updated 8 years ago
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆199Jan 10, 2024Updated 2 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆252Apr 10, 2023Updated 3 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆385Dec 27, 2023Updated 2 years ago
- A DNN Accelerator implemented with RTL.☆70Jan 9, 2025Updated last year