wzc810049078 / systolic-array-matrix-multiplierLinks
A systolic array matrix multiplier
☆24Updated 5 years ago
Alternatives and similar repositories for systolic-array-matrix-multiplier
Users that are interested in systolic-array-matrix-multiplier are comparing it to the libraries listed below
Sorting:
- ☆65Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago
- ☆34Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- ☆113Updated 5 years ago
- ☆31Updated 2 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆30Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- IC implementation of TPU☆128Updated 5 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆128Updated 2 months ago
- ☆27Updated 5 years ago
- ☆17Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆93Updated 2 weeks ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated 2 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆11Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆12Updated 4 years ago
- ☆43Updated 4 years ago