wzc810049078 / systolic-array-matrix-multiplierLinks
A systolic array matrix multiplier
☆29Updated 6 years ago
Alternatives and similar repositories for systolic-array-matrix-multiplier
Users that are interested in systolic-array-matrix-multiplier are comparing it to the libraries listed below
Sorting:
- ☆71Updated 6 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- ☆38Updated 6 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- ☆121Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆39Updated 3 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆143Updated 6 months ago
- ☆28Updated 6 years ago
- ☆19Updated 6 months ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- 3×3脉动阵列乘法器☆49Updated 6 years ago
- ☆66Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆120Updated 4 months ago
- ☆36Updated last month
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago