wzc810049078 / systolic-array-matrix-multiplierLinks
A systolic array matrix multiplier
☆26Updated 6 years ago
Alternatives and similar repositories for systolic-array-matrix-multiplier
Users that are interested in systolic-array-matrix-multiplier are comparing it to the libraries listed below
Sorting:
- ☆70Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆36Updated 3 years ago
- ☆120Updated 5 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- ☆37Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆173Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆14Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- 3×3脉动阵列乘法器☆46Updated 6 years ago
- IC implementation of TPU☆135Updated 5 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆34Updated last year
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆63Updated this week
- HLS implemented systolic array structure☆41Updated 7 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 5 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- Verilog implementation of Softmax function☆73Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆114Updated 3 months ago
- ☆35Updated last week