wzc810049078 / systolic-array-matrix-multiplierLinks
A systolic array matrix multiplier
☆25Updated 6 years ago
Alternatives and similar repositories for systolic-array-matrix-multiplier
Users that are interested in systolic-array-matrix-multiplier are comparing it to the libraries listed below
Sorting:
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆68Updated 6 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- ☆36Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- ☆119Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆59Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆13Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆172Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- ☆17Updated 4 months ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆34Updated 4 months ago
- vector accelerating unit☆34Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆27Updated last year
- IC implementation of TPU☆132Updated 5 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated 11 months ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- ☆27Updated 5 years ago
- ☆42Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆109Updated 2 months ago