wzc810049078 / systolic-array-matrix-multiplierLinks
A systolic array matrix multiplier
☆24Updated 5 years ago
Alternatives and similar repositories for systolic-array-matrix-multiplier
Users that are interested in systolic-array-matrix-multiplier are comparing it to the libraries listed below
Sorting:
- ☆65Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- ☆34Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- ☆27Updated 5 years ago
- ☆29Updated last month
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- ☆17Updated last month
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆29Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- ☆112Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆33Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Updated 6 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago