tirumalnaidu / opencl-hls-cnn-accelerator
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
☆74Updated last year
Related projects ⓘ
Alternatives and complementary repositories for opencl-hls-cnn-accelerator
- IC implementation of TPU☆86Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆102Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆71Updated this week
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆96Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆51Updated 2 years ago
- ☆60Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- IC implementation of Systolic Array for TPU☆148Updated 2 weeks ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆128Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆162Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆64Updated 3 months ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆81Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆38Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆46Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- ☆93Updated 4 years ago
- Verilog implementation of Softmax function☆47Updated 2 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆97Updated 4 years ago
- PYNQ Composabe Overlays☆67Updated 4 months ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆66Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆174Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 3 years ago