tirumalnaidu / opencl-hls-cnn-acceleratorLinks
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
☆79Updated last year
Alternatives and similar repositories for opencl-hls-cnn-accelerator
Users that are interested in opencl-hls-cnn-accelerator are comparing it to the libraries listed below
Sorting:
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- IC implementation of TPU☆128Updated 5 years ago
- ☆65Updated 6 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆139Updated 5 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆153Updated 2 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- Vitis HLS Library for FINN☆206Updated 3 weeks ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆106Updated 7 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- DPU on PYNQ☆226Updated 2 weeks ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- Hardware accelerator for convolutional neural networks☆50Updated 3 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- AMD University Program HLS tutorial☆100Updated 10 months ago
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆46Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆158Updated last year
- ☆58Updated 5 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago