linkuri267 / cnn_acceleratorLinks
CNN accelerator using NoC architecture
☆16Updated 6 years ago
Alternatives and similar repositories for cnn_accelerator
Users that are interested in cnn_accelerator are comparing it to the libraries listed below
Sorting:
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- ☆37Updated 6 years ago
- ☆14Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 10 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- ☆31Updated 5 years ago
- ☆27Updated 6 years ago
- A systolic array matrix multiplier☆28Updated 6 years ago
- NoC based MPSoC☆11Updated 11 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆24Updated last year
- Template for project1 TPU☆19Updated 4 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Updated 3 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- ☆13Updated 8 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆34Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago