Alternatives and similar repositories for cnn_accelerator

Users that are interested in cnn_accelerator are comparing it to the libraries listed below

• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆13Updated 2 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 8 years ago
• alireza-shirzad / Cordic_tanh
  Verilog and matlab implementation of tanh using Cordic algorithm
  ☆11Updated 5 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆14Updated 8 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆19Updated 7 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• gju06051 / TPU_HW_Verilog
  ☆14Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆36Updated 6 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 6 years ago
• eanchlia / NN_Network_On_Chip
  Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…
  ☆12Updated 6 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆42Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆36Updated 4 years ago
• freecores / an-fpga-implementation-of-low-latency-noc-based-mpsoc
  NoC based MPSoC
  ☆11Updated 11 years ago
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆14Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆29Updated 5 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆15Updated 9 months ago
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• Aquaticfuller / OpenExSys_CoherentCache
  OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
  ☆15Updated 6 months ago
• pulp-platform / hier-icache
  ☆13Updated 7 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆10Updated 2 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆25Updated 6 years ago
• mfkiwl / E203_dma
  ☆10Updated 5 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆38Updated 8 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago