CNN accelerator using NoC architecture
☆18Dec 6, 2018Updated 7 years ago
Alternatives and similar repositories for cnn_accelerator
Users that are interested in cnn_accelerator are comparing it to the libraries listed below
Sorting:
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- A verilog implementation for Network-on-Chip☆81Feb 3, 2018Updated 8 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆34Oct 23, 2025Updated 4 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆124Jul 22, 2020Updated 5 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- Network on Chip for MPSoC☆28Updated this week
- ☆12Nov 11, 2015Updated 10 years ago
- ☆13May 5, 2023Updated 2 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- ☆14Feb 24, 2025Updated last year
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- UVM testbench for verifying the Pulpino SoC☆12Mar 23, 2020Updated 5 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago