Digilent / Zybo-Z7-20-base-linux
☆16Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for Zybo-Z7-20-base-linux
- ☆52Updated 2 years ago
- Extensible FPGA control platform☆54Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆15Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- ☆23Updated 3 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- This store contains Configurable Example Designs.☆42Updated last week
- This is a circular buffer controller used in FPGA.☆33Updated 8 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- Networking Overlay on PYNQ☆44Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆56Updated 2 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- ☆48Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 10 months ago
- ☆34Updated 10 months ago
- RISCV model for Verilator/FPGA targets☆45Updated 5 years ago
- Open source FPGA-based NIC and platform for in-network compute☆58Updated 3 weeks ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆84Updated 5 years ago
- FuseSoC standard core library☆115Updated last month
- IP-core package generator for AXI4/Avalon☆21Updated 6 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆53Updated this week
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- 👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)☆14Updated 4 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- The multi-core cluster of a PULP system.☆56Updated last week
- SVA examples and demonstration☆16Updated 4 years ago