Digilent / Zybo-Z7-20-base-linuxLinks
☆16Updated 2 years ago
Alternatives and similar repositories for Zybo-Z7-20-base-linux
Users that are interested in Zybo-Z7-20-base-linux are comparing it to the libraries listed below
Sorting:
- ☆53Updated 2 years ago
- Demo SoC for SiliconCompiler.☆60Updated 2 weeks ago
- Extensible FPGA control platform☆62Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- FuseSoC standard core library☆147Updated 3 months ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆60Updated 5 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Mathematical Functions in Verilog☆94Updated 4 years ago
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- This store contains Configurable Example Designs.☆49Updated last week
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆184Updated 8 months ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆57Updated 3 months ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Verilog digital signal processing components☆151Updated 2 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- The multi-core cluster of a PULP system.☆108Updated this week
- FOS - FPGA Operating System☆71Updated 4 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆86Updated 3 weeks ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆89Updated 6 months ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- ☆40Updated last year