louislxw / pe_arrayLinks
A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as SCD and CNNs.
☆10Updated last year
Alternatives and similar repositories for pe_array
Users that are interested in pe_array are comparing it to the libraries listed below
Sorting:
- Reconfigurable Binary Engine☆16Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 10 months ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- CNN accelerator☆27Updated 7 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆19Updated last year
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last week
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- ☆27Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 8 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- ☆33Updated 6 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- ☆65Updated 6 years ago