louislxw / pe_arrayLinks
A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as SCD and CNNs.
☆13Updated last year
Alternatives and similar repositories for pe_array
Users that are interested in pe_array are comparing it to the libraries listed below
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆174Updated 5 years ago
- ☆120Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆233Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆89Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆118Updated 3 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆138Updated 6 months ago
- ☆41Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆32Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆37Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆59Updated 3 years ago
- IC implementation of TPU☆134Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆169Updated last year
- ☆71Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 10 months ago
- Deep Learning Accelerator (Convolution Neural Networks)☆195Updated 7 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- Verilog implementation of Softmax function☆75Updated 3 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆45Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆189Updated last year
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago