ignperez-udec / MobileNet-V2-inference-HLS
Codes to implement MobileNet V2 in a FPGA
☆25Updated 4 years ago
Alternatives and similar repositories for MobileNet-V2-inference-HLS:
Users that are interested in MobileNet-V2-inference-HLS are comparing it to the libraries listed below
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆28Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- ☆26Updated 2 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆23Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- ☆29Updated 3 years ago
- ☆52Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- a project build the SSD net in pynq-z2☆15Updated 4 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆14Updated 9 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆33Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆38Updated 5 years ago
- ☆21Updated 2 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆112Updated 4 years ago
- ☆11Updated last year
- ☆45Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 5 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago