19801201 / SpinalHDL_CNN_AcceleratorLinks
CNN accelerator implemented with Spinal HDL
☆152Updated last year
Alternatives and similar repositories for SpinalHDL_CNN_Accelerator
Users that are interested in SpinalHDL_CNN_Accelerator are comparing it to the libraries listed below
Sorting:
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆129Updated 3 months ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆352Updated last year
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆256Updated 7 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- ☆62Updated 2 years ago
- ☆43Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆190Updated 7 years ago
- IC implementation of Systolic Array for TPU☆269Updated 10 months ago
- 一个开源的FPGA神经网络加速器。☆172Updated last year
- A DNN Accelerator implemented with RTL.☆67Updated 7 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆153Updated 2 years ago
- ☆113Updated 5 years ago
- FPGA☆158Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆139Updated 5 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆95Updated last month
- some interesting demos for starters☆82Updated 2 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆191Updated 9 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆159Updated 2 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆238Updated 6 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated 2 years ago
- ☆10Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆158Updated last year
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago