19801201 / SpinalHDL_CNN_Accelerator
CNN accelerator implemented with Spinal HDL
☆144Updated last year
Alternatives and similar repositories for SpinalHDL_CNN_Accelerator:
Users that are interested in SpinalHDL_CNN_Accelerator are comparing it to the libraries listed below
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆163Updated 10 months ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆132Updated 2 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆175Updated last year
- IC implementation of Systolic Array for TPU☆178Updated 3 months ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆319Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆194Updated last year
- PYNQ学习资料☆160Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆212Updated 6 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆73Updated last year
- AXI总线连接器☆93Updated 4 years ago
- FPGA☆144Updated 7 months ago
- some interesting demos for starters☆68Updated 2 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆135Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆130Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆218Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆130Updated 2 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆68Updated 6 years ago
- 一个开源的FPGA神经网络加速器。☆139Updated last year
- ☆205Updated 9 months ago
- Deep Learning Accelerator (Convolution Neural Networks)☆170Updated 7 years ago
- image processing based FPGA☆100Updated 3 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆32Updated 3 years ago
- ☆59Updated 2 years ago
- CPU Design Based on RISCV ISA☆84Updated 7 months ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆12Updated 8 months ago