19801201 / SpinalHDL_CNN_AcceleratorLinks
CNN accelerator implemented with Spinal HDL
☆157Updated last year
Alternatives and similar repositories for SpinalHDL_CNN_Accelerator
Users that are interested in SpinalHDL_CNN_Accelerator are comparing it to the libraries listed below
Sorting:
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆240Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆178Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆167Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆194Updated last year
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆379Updated 2 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 8 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- ☆46Updated 5 years ago
- 一个开源的FPGA神经网络加速器。☆184Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆160Updated 10 months ago
- ☆124Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆177Updated last year
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆247Updated 7 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆126Updated 5 months ago
- IC implementation of Systolic Array for TPU☆319Updated last year
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆284Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆152Updated 8 months ago
- A DNN Accelerator implemented with RTL.☆68Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆218Updated 3 months ago
- FPGA☆159Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- AXI总线连接器☆105Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆61Updated 3 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago
- IC implementation of TPU☆144Updated 6 years ago