CNN accelerator implemented with Spinal HDL
☆159Jan 29, 2024Updated 2 years ago
Alternatives and similar repositories for SpinalHDL_CNN_Accelerator
Users that are interested in SpinalHDL_CNN_Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Jan 3, 2022Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆36Mar 14, 2021Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆18Dec 27, 2021Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆69Jan 8, 2024Updated 2 years ago
- An High-Performance SLAM Hardware Accelerator Implementation for FPGA☆73Nov 10, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- Scala based HDL☆1,977Apr 23, 2026Updated last week
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆22May 6, 2024Updated last year
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆385Dec 27, 2023Updated 2 years ago
- SpinalHDL Hardware Math Library☆99Jul 12, 2024Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆27Apr 22, 2026Updated last week
- Labs to learn SpinalHDL☆157Jul 4, 2024Updated last year
- List of SpinalHDL projects, libraries, and learning resources.☆29Jan 6, 2026Updated 3 months ago
- ☆10Apr 4, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆280Apr 1, 2024Updated 2 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆174Jul 25, 2019Updated 6 years ago
- SpinalHDL - Cryptography libraries☆60Jul 19, 2024Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆55Feb 2, 2026Updated 3 months ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- ☆23Feb 15, 2023Updated 3 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆26Nov 9, 2022Updated 3 years ago
- ☆16Dec 4, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- An out-of-order processor that supports multiple instruction sets.☆22Aug 23, 2022Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆19Jul 9, 2024Updated last year
- Open source machine learning accelerators☆397Mar 24, 2024Updated 2 years ago
- 基于FPGA量化的人脸口罩检测☆23Aug 24, 2021Updated 4 years ago
- xkISP：Xinkai ISP IP Core (HLS)☆313Mar 14, 2023Updated 3 years ago
- A basic SpinalHDL project☆95Aug 15, 2025Updated 8 months ago
- The hardware implementation of Poseidon hash function in SpinalHDL☆21Jun 5, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆313Jan 23, 2026Updated 3 months ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆130Aug 27, 2024Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆72Dec 29, 2025Updated 4 months ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆171Mar 5, 2025Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆152Jun 14, 2024Updated last year
- 基于verilog实现了ISP图像处理IP☆328Nov 28, 2022Updated 3 years ago
- Berkeley's Spatial Array Generator☆1,294Mar 29, 2026Updated last month