An LeNet RTL implement onto FPGA
☆51May 4, 2018Updated 7 years ago
Alternatives and similar repositories for LeNet_RTL
Users that are interested in LeNet_RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA/AES/LeNet/VGG16☆108Sep 9, 2018Updated 7 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Jun 30, 2020Updated 5 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 3 years ago
- Simulating implement of LeNet network on Zynq-7020 FPGA☆29Mar 11, 2019Updated 7 years ago
- FPGA实现动态图像识别☆23Jul 31, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆258Dec 29, 2018Updated 7 years ago
- 本工程使用纯verilog编写rtl代码，在FPGA上搭建神经网络LeNet-5，实现手写数字识别的功能。☆39Nov 18, 2024Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆196Mar 20, 2024Updated 2 years ago
- ☆14Nov 11, 2015Updated 10 years ago
- 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用☆591Jun 18, 2018Updated 7 years ago
- DMA core compatible with AHB3-Lite☆13Mar 30, 2019Updated 7 years ago
- ☆11Oct 10, 2019Updated 6 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- FPGA☆160Jun 29, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆19Mar 6, 2025Updated last year
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆372May 2, 2023Updated 3 years ago
- ☆17Apr 6, 2022Updated 4 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆166Dec 13, 2020Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆70Jan 9, 2025Updated last year
- ☆14May 15, 2023Updated 2 years ago
- FPGA Accelerator for CNN using Vivado HLS☆340Oct 25, 2021Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆49Oct 24, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR☆148Jul 20, 2023Updated 2 years ago
- using xilinx xc6slx45 to implement mnist net☆83Jul 5, 2018Updated 7 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆912Jul 29, 2024Updated last year
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- CNN acceleration on virtex-7 FPGA with verilog HDL☆482Feb 27, 2018Updated 8 years ago
- Implementation of CNN using Verilog☆246Oct 13, 2017Updated 8 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- SystemC to Verilog Synthesizable Subset Translator☆13May 12, 2023Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 10 years ago
- ov5640_sdram_vga_FPGA☆10Mar 27, 2023Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Using LSTM RNN to forecast time series; includes sine wave, electrocardiogram and ad impression forecasting☆11Aug 26, 2016Updated 9 years ago
- Convolution Neural Network of vgg19 model in verilog☆50Jan 4, 2018Updated 8 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- 基于FPGA的cifar-10二维卷积识别任务☆13Sep 8, 2022Updated 3 years ago