☆19Mar 21, 2023Updated 2 years ago
Alternatives and similar repositories for DPACS
Users that are interested in DPACS are comparing it to the libraries listed below
Sorting:
- ☆35Jul 9, 2020Updated 5 years ago
- ☆12Nov 24, 2023Updated 2 years ago
- ☆32Mar 31, 2025Updated 11 months ago
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- ☆21May 14, 2025Updated 9 months ago
- ☆21Oct 26, 2022Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Jul 9, 2024Updated last year
- ☆26Dec 12, 2022Updated 3 years ago
- ☆15Nov 11, 2024Updated last year
- Multimedia SoC Design with Specialization on Application Acceleration with High-Level-Synthesis [2020 Fall]☆12Jun 15, 2021Updated 4 years ago
- ☆13Jul 10, 2024Updated last year
- NeuraChip Accelerator Simulator☆16Apr 26, 2024Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- ☆29Nov 5, 2021Updated 4 years ago
- ☆14Apr 8, 2025Updated 10 months ago
- ☆15Jul 7, 2020Updated 5 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 6 years ago
- ☆15Nov 12, 2023Updated 2 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆19Jan 17, 2025Updated last year
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Jan 3, 2022Updated 4 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆16Aug 29, 2021Updated 4 years ago
- ☆35Mar 1, 2019Updated 7 years ago
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- Simulator for BitFusion☆101Aug 6, 2020Updated 5 years ago
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆20Aug 24, 2025Updated 6 months ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- HLS implemented systolic array structure☆41Nov 13, 2017Updated 8 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆133May 10, 2024Updated last year
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Apr 4, 2022Updated 3 years ago
- ☆65Apr 30, 2025Updated 10 months ago
- ☆19Mar 17, 2021Updated 4 years ago
- ☆44Jun 30, 2024Updated last year
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆23Mar 17, 2021Updated 4 years ago
- This repo contains the code for studying the interplay between quantization and sparsity methods☆26Feb 26, 2025Updated last year
- ViTALiTy (HPCA'23) Code Repository☆23Mar 13, 2023Updated 2 years ago
- Codes to implement MobileNet V2 in a FPGA☆28Dec 21, 2020Updated 5 years ago