USB Full Speed PHY
☆49May 3, 2020Updated 6 years ago
Alternatives and similar repositories for core_usb_fs_phy
Users that are interested in core_usb_fs_phy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Basic USB 1.1 Host Controller for small FPGAs☆104Jun 6, 2020Updated 6 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆49Jan 14, 2021Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆94May 15, 2021Updated 5 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆50Jun 19, 2024Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆71May 8, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Ethernet MAC 10/100 Mbps☆39Oct 31, 2021Updated 4 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 7 years ago
- USB 1.1 PHY☆11Jul 17, 2014Updated 12 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆40Dec 4, 2020Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆52Oct 24, 2021Updated 4 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 6 years ago
- Various HDL (Verilog) IP Cores☆934Jul 1, 2021Updated 5 years ago
- ULPI Link Wrapper (USB Phy Interface)☆39May 3, 2020Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- USB 2.0 Device IP Core☆75Oct 1, 2017Updated 8 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆27Mar 8, 2026Updated 6 months ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 6 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- ☆24Jun 17, 2014Updated 12 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 12 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆32Aug 16, 2021Updated 5 years ago
- Verilog SDRAM memory controller☆382May 13, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- USB serial device (CDC-ACM)☆49Jun 28, 2020Updated 6 years ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 5 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.☆13May 28, 2015Updated 11 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- okl4 git for porting to realview_eb RTSM platform☆15Oct 17, 2012Updated 13 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- ☆14Dec 17, 2015Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆42Sep 21, 2021Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆104Jun 6, 2020Updated 6 years ago
- Wishbone SATA Controller☆28Updated this week
- Minimal DVI / HDMI Framebuffer☆87Aug 9, 2020Updated 6 years ago
- Connecting SystemC with SystemVerilog☆43Mar 25, 2012Updated 14 years ago
- xk265：HEVC/H.265 Video Encoder IP Core (RTL)☆287Apr 9, 2023Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago