Alternatives and similar repositories for core_usb_fs_phy

Users that are interested in core_usb_fs_phy are comparing it to the libraries listed below

• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 8 months ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆80Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆45Updated 3 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆41Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆95Updated 5 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆69Updated 8 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆36Updated 6 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 5 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆29Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆78Updated 2 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆33Updated 4 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 7 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆23Updated 11 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆89Updated 2 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆53Updated 10 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 10 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 8 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated 4 months ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 6 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 9 years ago