Alternatives and similar repositories for core_usb_fs_phy

Users that are interested in core_usb_fs_phy are comparing it to the libraries listed below

• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆81Updated 4 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆91Updated 5 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 7 months ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆41Updated 3 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆68Updated 7 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆37Updated 6 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆40Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆76Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆29Updated 5 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 5 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆95Updated 5 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 7 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆87Updated 2 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 5 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆52Updated 9 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 7 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆61Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆85Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 6 months ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆96Updated 5 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆80Updated last year
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• freecores / uart16550
  UART 16550 core
  ☆37Updated 11 years ago