USB Full Speed PHY
☆49May 3, 2020Updated 5 years ago
Alternatives and similar repositories for core_usb_fs_phy
Users that are interested in core_usb_fs_phy are comparing it to the libraries listed below
Sorting:
- Basic USB 1.1 Host Controller for small FPGAs☆98Jun 6, 2020Updated 5 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Jan 14, 2021Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆88May 15, 2021Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Jun 19, 2024Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆33Oct 31, 2021Updated 4 years ago
- FPGA USB 1.1 Low-Speed Implementation☆35Oct 3, 2018Updated 7 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- USB 1.1 PHY☆11Jul 17, 2014Updated 11 years ago
- ULPI Link Wrapper (USB Phy Interface)☆36May 3, 2020Updated 5 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Dec 4, 2020Updated 5 years ago
- Various HDL (Verilog) IP Cores☆879Jul 1, 2021Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆48Oct 24, 2021Updated 4 years ago
- USB 2.0 Device IP Core☆74Oct 1, 2017Updated 8 years ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 5 months ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Mar 8, 2026Updated 2 weeks ago
- ☆21Jun 17, 2014Updated 11 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 5 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Mar 22, 2023Updated 3 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆29Aug 16, 2021Updated 4 years ago
- Verilog SDRAM memory controller☆363May 13, 2017Updated 8 years ago
- USB serial device (CDC-ACM)☆45Jun 28, 2020Updated 5 years ago
- VHDL simulation model for PADAUK PDK microcontrollers☆21May 20, 2020Updated 5 years ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 7 years ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 6 years ago
- A Time to Digital Converter designed for Xilinx 7-Series FPGAs☆36Jan 21, 2021Updated 5 years ago
- ☆14Dec 17, 2015Updated 10 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Jun 6, 2020Updated 5 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Sep 21, 2021Updated 4 years ago
- Connecting SystemC with SystemVerilog☆42Mar 25, 2012Updated 13 years ago
- Minimal DVI / HDMI Framebuffer☆83Aug 9, 2020Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- xk265：HEVC/H.265 Video Encoder IP Core (RTL)☆271Apr 9, 2023Updated 2 years ago