ultraembedded / core_soc
Basic Peripheral SoC (SPI, GPIO, Timer, UART)
☆58Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for core_soc
- UART -> AXI Bridge☆57Updated 3 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 9 years ago
- AMBA bus generator including AXI, AHB, and APB☆90Updated 3 years ago
- ☆34Updated 9 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- IP operations in verilog (simulation and implementation on ice40)☆52Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆58Updated 2 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆68Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 6 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- Verilog SPI master and slave☆46Updated 8 years ago
- PCIE 5.0 Graduation project (Verification Team)☆55Updated 9 months ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆114Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆40Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆29Updated 2 years ago
- Implementation of the PCIe physical layer☆30Updated last week