Basic Peripheral SoC (SPI, GPIO, Timer, UART)
☆71May 8, 2020Updated 6 years ago
Alternatives and similar repositories for core_soc
Users that are interested in core_soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- UART -> AXI Bridge☆78Jul 1, 2021Updated 5 years ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 6 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆16Dec 29, 2016Updated 9 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Various HDL (Verilog) IP Cores☆934Jul 1, 2021Updated 5 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 7 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- General Purpose IO with APB4 interface☆17May 10, 2024Updated 2 years ago
- ☆14Dec 17, 2015Updated 10 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆89Dec 7, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- APB Timer Unit☆14Oct 30, 2025Updated 10 months ago
- USB capture IP☆27Jun 6, 2020Updated 6 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- The UVM written in Python☆18Updated this week
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Jan 14, 2018Updated 8 years ago
- ☆38Aug 12, 2015Updated 11 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 12 years ago
- AXI DMA 32 / 64 bits☆128Jul 17, 2014Updated 12 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 12 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A simple implementation of a UART modem in Verilog.☆195Nov 10, 2021Updated 4 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 6 years ago
- ARM中通过APB总线连接的UART模块☆72Feb 21, 2020Updated 6 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆632Oct 10, 2021Updated 4 years ago
- AHB DMA 32 / 64 bits☆64Jul 17, 2014Updated 12 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- HW JPEG decoder wrapper with AXI-4 DMA☆40Oct 25, 2020Updated 5 years ago
- High Speed USB 2.0 capture device based on miniSpartan6+☆60May 26, 2020Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆27Mar 8, 2026Updated 6 months ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆49Jan 14, 2021Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago