CospanDesign / verilog_ppfifo_demo
Simple demo showing how to use the ping pong FIFO
☆13Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for verilog_ppfifo_demo
- ☆16Updated 5 years ago
- Direct Access Memory for MPSoC☆12Updated 3 weeks ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- RTL code of some arbitration algorithm☆12Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- Generic AXI master stub☆19Updated 10 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- 位宽和深度可定制的异步FIFO☆12Updated 5 months ago
- NoC based MPSoC☆10Updated 10 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆17Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆13Updated 3 months ago
- FIR,FFT based on Verilog☆13Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆12Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆9Updated last year
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆10Updated 3 weeks ago
- JPEG Compression RTL implementation☆9Updated 7 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- a hardware task scheduler design☆9Updated 2 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- The template for VLSI project☆15Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- Implementation of the PCIe physical layer☆30Updated last week