wmy367 / Radix-2-divisionLinks
unsigned Radix-2 SRT division,基2除法
☆15Updated 10 years ago
Alternatives and similar repositories for Radix-2-division
Users that are interested in Radix-2-division are comparing it to the libraries listed below
Sorting:
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- ☆21Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated this week
- Generic AXI master stub☆19Updated 11 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 6 months ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆10Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- General Purpose AXI Direct Memory Access☆57Updated last year
- ☆29Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Implementation of the PCIe physical layer☆47Updated last month
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- NoC based MPSoC☆11Updated 11 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 8 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- ☆20Updated 5 years ago
- Contains commonly used UVM components (agents, environments and tests).☆29Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆35Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago