wmy367 / Radix-2-divisionLinks
unsigned Radix-2 SRT division,基2除法
☆16Updated 10 years ago
Alternatives and similar repositories for Radix-2-division
Users that are interested in Radix-2-division are comparing it to the libraries listed below
Sorting:
- SystemVerilog IPs and Modules for architectural redundancy designs.☆16Updated last month
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 3 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- ☆22Updated 6 years ago
- ☆31Updated 5 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- The memory model was leveraged from micron.☆25Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- APB Logic☆22Updated last month
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- ☆33Updated last month
- verification of simple axi-based cache☆18Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆33Updated 3 weeks ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Generic AXI master stub☆19Updated 11 years ago
- ☆10Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- ☆20Updated 11 years ago
- A Verilog implementation of a processor cache.☆34Updated 8 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- Simple single-port AXI memory interface☆49Updated last year
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated 2 months ago
- Python Tool for UVM Testbench Generation☆55Updated last year