Basic USB-CDC device core (Verilog)
☆88May 15, 2021Updated 4 years ago
Alternatives and similar repositories for core_usb_cdc
Users that are interested in core_usb_cdc are comparing it to the libraries listed below
Sorting:
- USB serial device (CDC-ACM)☆45Jun 28, 2020Updated 5 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆237Oct 30, 2022Updated 3 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 5 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆187Mar 10, 2024Updated 2 years ago
- An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA comm…☆865Dec 6, 2024Updated last year
- Cheapest UAC2 using STM32F407+USB3300☆21Feb 26, 2025Updated last year
- fork from https://gitee.com/crouchggj/STM32F4_USB_SoundCard☆16Aug 3, 2019Updated 6 years ago
- Various HDL (Verilog) IP Cores☆879Jul 1, 2021Updated 4 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- a USB2 highspeed device core, written in amaranth HDL☆53Sep 17, 2024Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆98Jun 6, 2020Updated 5 years ago
- USB 2.0 Device IP Core☆74Oct 1, 2017Updated 8 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆33Oct 31, 2021Updated 4 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Dec 2, 2018Updated 7 years ago
- A simple 6502 system built on a Lattice Ultra Plus 5k FPGA☆15Mar 11, 2019Updated 7 years ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- USB 1.1 Host and Function IP core☆25Jul 17, 2014Updated 11 years ago
- Nitro USB FPGA core☆86Mar 1, 2026Updated 2 weeks ago
- Audio controller (I2S, SPDIF, DAC)☆95Sep 1, 2019Updated 6 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆30May 10, 2020Updated 5 years ago
- Open Source Windows UAC2 driver☆20Feb 24, 2013Updated 13 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆78Apr 11, 2022Updated 3 years ago
- The DDR Test Firmware for LicheeTang20K.☆17Jun 20, 2023Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆78Jan 2, 2021Updated 5 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆575Oct 10, 2021Updated 4 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Jun 5, 2021Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆43Apr 11, 2024Updated last year
- A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA☆29Jun 12, 2019Updated 6 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- RISC-V CSR Access Routines☆15Dec 27, 2022Updated 3 years ago
- ☆10Mar 18, 2020Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- WISHBONE SD Card Controller IP Core☆131Sep 17, 2022Updated 3 years ago