amiq-consulting / amiq_ofc
Open-Source Framework for Co-Emulation
☆11Updated 4 years ago
Alternatives and similar repositories for amiq_ofc:
Users that are interested in amiq_ofc are comparing it to the libraries listed below
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 4 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 9 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- Systemverilog DPI-C call Python function☆22Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Useful UVM extensions☆21Updated 8 months ago
- Common SystemVerilog RTL modules for RgGen☆12Updated last month
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 10 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- Python/Simulator integration using procedure calls☆9Updated 5 years ago
- UVM Python Verification Agents Library☆14Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- ☆15Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- APB Logic☆15Updated 3 months ago
- Various low power labs using sky130☆11Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆15Updated 10 months ago
- A mock framework for use with SVUnit☆16Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆14Updated 2 months ago
- UVM Clock and Reset Agent☆13Updated 7 years ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆35Updated 9 months ago