amiq-consulting / amiq_ofcLinks
Open-Source Framework for Co-Emulation
☆12Updated 4 years ago
Alternatives and similar repositories for amiq_ofc
Users that are interested in amiq_ofc are comparing it to the libraries listed below
Sorting:
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 9 months ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆49Updated 2 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 4 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Updated 3 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated last month
- UART cocotb module☆11Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- A mock framework for use with SVUnit☆18Updated 2 years ago
- Python interface for cross-calling with HDL☆39Updated 3 weeks ago
- SystemVerilog FSM generator☆32Updated last year
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆12Updated 3 years ago
- ☆29Updated 2 weeks ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆14Updated last month
- A header only C++11 library for functional coverage☆36Updated 3 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 5 years ago
- SystemVerilog Logger☆18Updated last week
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆36Updated last year
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Updated 5 years ago
- ☆13Updated 3 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆26Updated 7 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 5 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year