amiq-consulting / amiq_ofcLinks
Open-Source Framework for Co-Emulation
☆12Updated 4 years ago
Alternatives and similar repositories for amiq_ofc
Users that are interested in amiq_ofc are comparing it to the libraries listed below
Sorting:
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 weeks ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 3 months ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆49Updated last month
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 5 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆25Updated 4 years ago
- Import and export IP-XACT XML register models☆35Updated this week
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 4 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- ☆13Updated 3 years ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- ☆29Updated last month
- SystemVerilog RTL and UVM RAL model generators for RgGen☆14Updated last month
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- Cross EDA Abstraction and Automation☆39Updated 2 weeks ago
- Python interface for cross-calling with HDL☆35Updated last week
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Updated last year
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- SystemVerilog FSM generator☆32Updated last year
- Platform Level Interrupt Controller☆42Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated last year