amiq-consulting / amiq_ofcLinks
Open-Source Framework for Co-Emulation
☆12Updated 4 years ago
Alternatives and similar repositories for amiq_ofc
Users that are interested in amiq_ofc are comparing it to the libraries listed below
Sorting:
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆12Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆34Updated 7 months ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆48Updated this week
- SystemVerilog RTL and UVM RAL model generators for RgGen☆14Updated 3 weeks ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated last year
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 2 months ago
- SystemVerilog FSM generator☆32Updated last year
- UVM Python Verification Agents Library☆14Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- SystemVerilog Logger☆18Updated 2 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Useful UVM extensions☆24Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆26Updated 5 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- ☆12Updated 2 years ago
- Python interface for cross-calling with HDL☆34Updated last week
- Advanced Debug Interface☆15Updated 6 months ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- ☆30Updated 2 weeks ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆25Updated 4 years ago
- Open Source PHY v2☆29Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- ☆14Updated 2 months ago
- A CSV file parser, written in SystemVerilog☆26Updated 9 years ago