Alternatives and similar repositories for amiq_ofc:

Users that are interested in amiq_ofc are comparing it to the libraries listed below

• seabeam / yuu_clock
  UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
  ☆10Updated 4 years ago
• amiq-consulting / cagt
  Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …
  ☆12Updated 9 years ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆22Updated 4 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated last month
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 5 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆31Updated 2 months ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 5 years ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆15Updated last year
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆14Updated 3 years ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 5 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆31Updated this week
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆24Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated 2 weeks ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆23Updated 4 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆18Updated 6 months ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆23Updated 2 weeks ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆13Updated last month
• pulp-platform / apb
  APB Logic
  ☆15Updated 3 months ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆19Updated 7 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆21Updated 8 months ago
• bluwireless / blade
  Hardware Design, Exploration, and Code Generation for SoC Designers
  ☆10Updated 5 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆12Updated 9 years ago
• rggen / rggen-sample-testbench
  ☆14Updated 3 weeks ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated 2 weeks ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 7 years ago