amiq-consulting / amiq_ofcLinks
Open-Source Framework for Co-Emulation
☆12Updated 4 years ago
Alternatives and similar repositories for amiq_ofc
Users that are interested in amiq_ofc are comparing it to the libraries listed below
Sorting:
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- CORE-V MCU UVM Environment and Test Bench☆22Updated last year
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 2 months ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 5 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆28Updated last year
- ☆12Updated 3 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Updated 5 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Updated last year
- SystemVerilog FSM generator☆32Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆26Updated 6 months ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆49Updated 3 weeks ago
- A mock framework for use with SVUnit☆18Updated 2 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆14Updated last week
- UVM Python Verification Agents Library☆15Updated 4 years ago
- ☆30Updated last week
- SystemVerilog Logger☆18Updated 2 years ago
- Python interface for cross-calling with HDL☆35Updated 2 weeks ago
- Platform Level Interrupt Controller☆41Updated last year
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆12Updated 2 years ago
- Useful UVM extensions☆24Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 7 months ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago