dineshannayya / yifive_r0
A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
☆18Updated 2 years ago
Alternatives and similar repositories for yifive_r0:
Users that are interested in yifive_r0 are comparing it to the libraries listed below
- ☆19Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Python Tool for UVM Testbench Generation☆51Updated 10 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 10 months ago
- ☆25Updated 3 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 4 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated 3 weeks ago
- UART -> AXI Bridge☆60Updated 3 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- ☆16Updated 5 years ago
- ☆21Updated 5 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 4 months ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 8 years ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated last month
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- Open FPGA Modules☆23Updated 5 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 10 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- WISHBONE Interconnect☆11Updated 7 years ago