A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
☆22Mar 22, 2023Updated 3 years ago
Alternatives and similar repositories for yifive_r0
Users that are interested in yifive_r0 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Mar 28, 2025Updated last year
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Nov 17, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA☆14Nov 24, 2014Updated 11 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 2 years ago
- Dual-Core Out-of-Order MIPS CPU Design☆22May 8, 2025Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆23Apr 30, 2026Updated last week
- Mini RISC-V SOC☆12Nov 13, 2015Updated 10 years ago
- ☆15Jul 14, 2024Updated last year
- simple hyperram controller☆12Feb 10, 2019Updated 7 years ago
- Arduino compatible Risc-V Based SOC☆160Jul 14, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated 2 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- RTL modbus rtu slave for FPGA☆14Apr 29, 2022Updated 4 years ago
- Modbus block on FPGA☆14Jul 24, 2020Updated 5 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆18Oct 24, 2014Updated 11 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 6 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆30Aug 16, 2021Updated 4 years ago
- ☆65Dec 16, 2018Updated 7 years ago
- ☆17Jun 5, 2024Updated last year
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Sep 21, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FPGA state machine for minimalistic USB HID device hosting☆15Aug 27, 2022Updated 3 years ago
- A toy c compiler written in python☆11Jan 9, 2024Updated 2 years ago
- ☆20Dec 27, 2024Updated last year
- FPGA纯逻辑实现modbus通信☆23Sep 5, 2022Updated 3 years ago
- ☆12May 15, 2022Updated 3 years ago
- Fixed Point Kalman filter for fpga☆25May 10, 2020Updated 5 years ago
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆23Jan 24, 2026Updated 3 months ago
- D3.js based wave (signal) visualizer☆68Aug 19, 2025Updated 8 months ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- HF-RISC SoC☆39Mar 22, 2026Updated last month
- This is the base repo for our graduation project in AlexU 21☆28Jul 26, 2021Updated 4 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆44May 12, 2016Updated 9 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago