ultraembedded / core_spiflashLinks
SPI-Flash XIP Interface (Verilog)
☆47Updated 4 years ago
Alternatives and similar repositories for core_spiflash
Users that are interested in core_spiflash are comparing it to the libraries listed below
Sorting:
- USB 2.0 Device IP Core☆72Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Small (Q)SPI flash memory programmer in Verilog☆67Updated 3 years ago
- Verilog SPI master and slave☆62Updated 9 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- UART -> AXI Bridge☆67Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆82Updated last year
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆81Updated last year
- Ethernet MAC 10/100 Mbps☆29Updated 4 years ago
- Basic USB-CDC device core (Verilog)☆82Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆93Updated 3 years ago
- QSPI for SoC☆23Updated 6 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆74Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated 11 months ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- Testbenches for HDL projects☆22Updated this week
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated last month
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆76Updated last year
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- AXI-4 RAM Tester Component☆20Updated 5 years ago