SPI-Flash XIP Interface (Verilog)
☆52Oct 24, 2021Updated 4 years ago
Alternatives and similar repositories for core_spiflash
Users that are interested in core_spiflash are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ethernet MAC 10/100 Mbps☆39Oct 31, 2021Updated 4 years ago
- spi memory controller☆24Jan 5, 2017Updated 9 years ago
- Small (Q)SPI flash memory programmer in Verilog☆70Nov 5, 2022Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- This is a circular buffer controller used in FPGA.☆36Jan 12, 2016Updated 10 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 8 years ago
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 8 months ago
- Wishbone SATA Controller☆28Jul 9, 2026Updated 2 weeks ago
- Open Source SSD Controller. NVMe and Lightstor variants☆17May 21, 2014Updated 12 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆103Oct 31, 2022Updated 3 years ago
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆82Sep 14, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆11Oct 18, 2024Updated last year
- Open-Channel Open-Way Flash Controller☆25Sep 10, 2021Updated 4 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆36Nov 11, 2017Updated 8 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆88Sep 14, 2023Updated 2 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- USB -> AXI Debug Bridge☆45Jun 5, 2021Updated 5 years ago
- An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码器,可以从PNG文件中解码出原始像素。☆105Sep 14, 2023Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。☆137Sep 14, 2023Updated 2 years ago
- VHDL Modules☆24Mar 16, 2015Updated 11 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆39Oct 25, 2020Updated 5 years ago
- Hardware implementation of HDR image producing algorithm☆16Sep 30, 2022Updated 3 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆35Jun 5, 2021Updated 5 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来…☆105Sep 14, 2023Updated 2 years ago
- ☆16Dec 15, 2017Updated 8 years ago
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆123Sep 19, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 7 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆338Sep 14, 2023Updated 2 years ago
- Altera USB Blaster porting to Artery AT32F425 and WCH CH32V203.☆28Jun 7, 2025Updated last year
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆44Jun 6, 2024Updated 2 years ago
- Various HDL (Verilog) IP Cores☆924Jul 1, 2021Updated 5 years ago
- Yet Another Debug Transport☆30Jul 4, 2026Updated 2 weeks ago
- ☆35Jul 9, 2025Updated last year