ultraembedded / core_spiflashLinks
SPI-Flash XIP Interface (Verilog)
☆45Updated 4 years ago
Alternatives and similar repositories for core_spiflash
Users that are interested in core_spiflash are comparing it to the libraries listed below
Sorting:
- USB 2.0 Device IP Core☆70Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆75Updated last year
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- QSPI for SoC☆23Updated 5 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 4 years ago
- Verilog SPI master and slave☆60Updated 9 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆12Updated 8 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆90Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆28Updated 3 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆75Updated last year
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆68Updated 4 years ago
- 【例程】国产高云FPGA 开发板及其工程☆37Updated last year
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆29Updated 2 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆57Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆81Updated last year