ultraembedded / core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
☆93Updated 4 years ago
Alternatives and similar repositories for core_ft60x_axi:
Users that are interested in core_ft60x_axi are comparing it to the libraries listed below
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆66Updated 2 years ago
- Basic USB-CDC device core (Verilog)☆76Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆33Updated 11 months ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- IEEE P1735 decryptor for VHDL☆30Updated 9 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- ☆82Updated 7 years ago
- Verilog digital signal processing components☆129Updated 2 years ago
- Extensible FPGA control platform☆59Updated last year
- ☆60Updated 3 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- USB 2.0 Device IP Core☆61Updated 7 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- USB3 PIPE interface for Xilinx 7-Series☆209Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆59Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆75Updated 11 months ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆144Updated 2 weeks ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆50Updated 4 years ago
- Control and Status Register map generator for HDL projects☆110Updated 3 weeks ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- FPGA Logic Analyzer and GUI☆118Updated 2 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆122Updated 4 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆68Updated 9 months ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆39Updated 3 years ago