stffrdhrn / sdram-controller

Related projects: ⓘ

• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆344Updated 2 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆470Updated 8 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆403Updated last year
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆515Updated 2 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆684Updated 3 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆255Updated 4 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆243Updated 4 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆716Updated last month
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆272Updated 7 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆494Updated this week
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆247Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆358Updated last month
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆206Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆535Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆357Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,048Updated last month
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆208Updated 10 months ago
• jamieiles / uart
  Verilog UART
  ☆118Updated 11 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆515Updated last year
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆360Updated last year
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆114Updated 2 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆353Updated 2 months ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆396Updated 2 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆258Updated last month
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆228Updated 5 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆227Updated 11 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆376Updated last month
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆169Updated 4 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆244Updated 2 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆134Updated last year