Verilog SDRAM memory controller
☆377May 13, 2017Updated 9 years ago
Alternatives and similar repositories for sdram-controller
Users that are interested in sdram-controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog HDL implementation of SDRAM controller and SDRAM model☆47Jun 19, 2024Updated 2 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆623Oct 10, 2021Updated 4 years ago
- DDR2 memory controller written in Verilog☆84Feb 28, 2012Updated 14 years ago
- Various HDL (Verilog) IP Cores☆929Jul 1, 2021Updated 5 years ago
- Verilog I2C interface for FPGA implementation☆715Feb 27, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- Opensource DDR3 Controller☆466Jun 12, 2026Updated last month
- Verilog library for ASIC and FPGA designers☆1,435May 8, 2024Updated 2 years ago
- Verilog Ethernet components for FPGA implementation☆3,058Feb 27, 2025Updated last year
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- Verilog UART☆575Feb 27, 2025Updated last year
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆24Nov 17, 2021Updated 4 years ago
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 5 years ago
- Small footprint and configurable DRAM core☆532Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Verilog modules required to get the OV7670 camera working☆84Jul 26, 2018Updated 8 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆84Dec 1, 2022Updated 3 years ago
- DDR4 Simulation Project in System Verilog☆47Aug 18, 2014Updated 11 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆31Aug 16, 2021Updated 4 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆587Jun 6, 2026Updated 2 months ago
- Verilog AXI components for FPGA implementation☆2,109Feb 27, 2025Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆102Jun 6, 2020Updated 6 years ago
- Must-have verilog systemverilog modules☆2,006Mar 12, 2026Updated 4 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆242Oct 30, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The memory model was leveraged from micron.☆31Mar 24, 2018Updated 8 years ago
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。☆344Sep 14, 2023Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆86Sep 7, 2020Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆219Sep 15, 2023Updated 2 years ago
- Verilog implementation of Bresenham's line drawing algorithm.☆14May 11, 2026Updated 3 months ago
- AHB DMA 32 / 64 bits☆63Jul 17, 2014Updated 12 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆93Apr 8, 2024Updated 2 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆64Jan 8, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 使用verilog编写sdram控制器☆13Jun 22, 2019Updated 7 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆19Jul 25, 2023Updated 3 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆470Feb 13, 2026Updated 5 months ago
- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals☆258Nov 29, 2018Updated 7 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆90Oct 2, 2019Updated 6 years ago
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 4 years ago