Verilog SDRAM memory controller
☆368May 13, 2017Updated 9 years ago
Alternatives and similar repositories for sdram-controller
Users that are interested in sdram-controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog HDL implementation of SDRAM controller and SDRAM model☆42Jun 19, 2024Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆591Oct 10, 2021Updated 4 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 14 years ago
- Various HDL (Verilog) IP Cores☆902Jul 1, 2021Updated 4 years ago
- Verilog I2C interface for FPGA implementation☆701Feb 27, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- Opensource DDR3 Controller☆431Jan 18, 2026Updated 4 months ago
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- Verilog library for ASIC and FPGA designers☆1,415May 8, 2024Updated 2 years ago
- Verilog Ethernet components for FPGA implementation☆2,959Feb 27, 2025Updated last year
- Verilog UART☆562Feb 27, 2025Updated last year
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Nov 17, 2021Updated 4 years ago
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 5 years ago
- Verilog modules required to get the OV7670 camera working☆80Jul 26, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Small footprint and configurable DRAM core☆502May 12, 2026Updated last week
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆81Dec 1, 2022Updated 3 years ago
- DDR4 Simulation Project in System Verilog☆46Aug 18, 2014Updated 11 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆100Jun 6, 2020Updated 5 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆30Aug 16, 2021Updated 4 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆583Aug 21, 2025Updated 9 months ago
- Verilog AXI components for FPGA implementation☆2,044Feb 27, 2025Updated last year
- Must-have verilog systemverilog modules☆1,958Mar 12, 2026Updated 2 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆239Oct 30, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。☆338Sep 14, 2023Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆85Sep 7, 2020Updated 5 years ago
- The memory model was leveraged from micron.☆30Mar 24, 2018Updated 8 years ago
- Verilog implementation of Bresenham's line drawing algorithm.☆14May 11, 2026Updated last week
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。☆210Sep 15, 2023Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆89Apr 8, 2024Updated 2 years ago
- AHB DMA 32 / 64 bits☆61Jul 17, 2014Updated 11 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆64Jan 8, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆73Jul 25, 2023Updated 2 years ago
- 使用verilog编写sdram控制器☆13Jun 22, 2019Updated 6 years ago
- Computational Storage Device based on the open source project OpenSSD.☆31Oct 25, 2020Updated 5 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- FPGA GPU design for DE1-SoC☆72Dec 27, 2021Updated 4 years ago
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 4 years ago
- SDRAM controller with AXI4 interface☆104Aug 8, 2019Updated 6 years ago