ultraembedded / core_usb_uartLinks
USB serial device (CDC-ACM)
☆41Updated 5 years ago
Alternatives and similar repositories for core_usb_uart
Users that are interested in core_usb_uart are comparing it to the libraries listed below
Sorting:
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- USB 2.0 Device IP Core☆69Updated 8 years ago
- ULPI Link Wrapper (USB Phy Interface)☆29Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆33Updated 4 years ago
- FT2232HL JTAG & UART Downloader☆19Updated 4 years ago
- Wishbone controlled I2C controllers☆53Updated 10 months ago
- ☆50Updated 3 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆62Updated 6 years ago
- Xilinx virtual cable server for generic FTDI 4232H.☆59Updated last year
- SDIO Device Verilog Core☆22Updated 7 years ago
- Nitro USB FPGA core☆87Updated last year
- TCP/IP controlled VPI JTAG Interface.☆67Updated 8 months ago
- Audio controller (I2S, SPDIF, DAC)☆89Updated 6 years ago
- ☆46Updated 2 years ago
- Digital FM Radio Receiver for FPGA☆63Updated 9 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆45Updated 4 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆56Updated 2 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago