ultraembedded / core_usb_uart
USB serial device (CDC-ACM)
☆38Updated 4 years ago
Alternatives and similar repositories for core_usb_uart:
Users that are interested in core_usb_uart are comparing it to the libraries listed below
- Basic USB-CDC device core (Verilog)☆77Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- USB 2.0 Device IP Core☆66Updated 7 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- SDIO Device Verilog Core☆22Updated 6 years ago
- Small (Q)SPI flash memory programmer in Verilog☆62Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆43Updated 3 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 4 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- ☆45Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆77Updated last year
- Verilog Repository for GIT☆32Updated 4 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- Wishbone interconnect utilities☆40Updated 2 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- TCP/IP controlled VPI JTAG Interface.☆65Updated 3 months ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆80Updated 4 years ago
- Wishbone controlled I2C controllers☆49Updated 5 months ago
- Digilent JTAG clone hardware + eeprom firmware (.bin)☆62Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- Xilinx virtual cable server for generic FTDI 4232H.☆57Updated last year
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- ☆30Updated 8 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆69Updated 2 years ago