ultraembedded/core_usb_uart external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

ultraembedded/core_usb_uart

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/ultraembedded/core_usb_uart)

Close

ultraembedded / core_usb_uartView on GitHubMore

• External links
• Readme badge

USB serial device (CDC-ACM)

☆48Jun 28, 2020Updated 6 years ago

Alternatives and similar repositories for core_usb_uart

Users that are interested in core_usb_uart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• ultraembedded / core_usb_cdc

  View on GitHub
  Basic USB-CDC device core (Verilog)
  ☆93May 15, 2021Updated 5 years ago
• rushxrushx / stm32f4_usbaudio2

  View on GitHub
  Cheapest UAC2 using STM32F407+USB3300
  ☆22Feb 26, 2025Updated last year
• ultraembedded / core_ulpi_wrapper

  View on GitHub
  ULPI Link Wrapper (USB Phy Interface)
  ☆38May 3, 2020Updated 6 years ago
• DaveBerkeley / fpga

  View on GitHub
  Verilog FPGA code : including experimental DSP audio processor
  ☆14Dec 1, 2020Updated 5 years ago
• ultraembedded / ecpix-5

  View on GitHub
  Projects for the ECPiX-5 - a ECP5 FPGA board.
  ☆14Jul 5, 2020Updated 6 years ago
• 1-Click AI Models by DigitalOcean Gradient • Ad
  Deploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
• coflery / STM32F4_USB_SoundCard

  View on GitHub
  fork from https://gitee.com/crouchggj/STM32F4_USB_SoundCard
  ☆17Aug 3, 2019Updated 7 years ago
• ultraembedded / riscv_sbc

  View on GitHub
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆31May 10, 2020Updated 6 years ago
• ultraembedded / usb2sniffer

  View on GitHub
  USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
  ☆59Jun 6, 2020Updated 6 years ago
• ultraembedded / core_usb_sniffer

  View on GitHub
  USB capture IP
  ☆27Jun 6, 2020Updated 6 years ago
• hydrausb3 / wch-ch569-serdes

  View on GitHub
  WCH CH569 SerDes Reverse Engineering
  ☆30Aug 13, 2022Updated 4 years ago
• borgestrand / winuac2

  View on GitHub
  Open Source Windows UAC2 driver
  ☆21Feb 24, 2013Updated 13 years ago
• kazkojima / lunauac2-pdm

  View on GitHub
  A LiteX module implementing a USB UAC2 module with simple PDM in/out
  ☆16Feb 16, 2022Updated 4 years ago
• awygle / waggle

  View on GitHub
  Rust proof-of-concept for GPU waveform rendering
  ☆13Jul 22, 2020Updated 6 years ago
• ultraembedded / core_usb_host

  View on GitHub
  Basic USB 1.1 Host Controller for small FPGAs
  ☆104Jun 6, 2020Updated 6 years ago
• Managed Kubernetes at scale on DigitalOcean • Ad
  DigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
• ramanmangla / Digital-Audio-Equalizer

  View on GitHub
  Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.
  ☆12Aug 9, 2019Updated 7 years ago
• FlorentCLMichel / karatsuba_multiplication_verilog

  View on GitHub
  A simple implementation of the Karatsuba multiplication algorithm
  ☆12Apr 2, 2025Updated last year
• ultraembedded / core_ftdi_bridge

  View on GitHub
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆35Jun 5, 2021Updated 5 years ago
• knielsen / ice40-stm32-sdram

  View on GitHub
  Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA
  ☆30Dec 19, 2016Updated 9 years ago
• jpt13653903 / FUI-Audio-DAC

  View on GitHub
  FPGA-Based USB-Input Audio Digital to Analogue Converter
  ☆17Jun 11, 2021Updated 5 years ago
• defparam / PCI2Nano-RTL

  View on GitHub
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆49Jan 14, 2021Updated 5 years ago
• AngeloJacobo / FPGA_SDRAM_Controller

  View on GitHub
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆31Aug 16, 2021Updated 5 years ago
• ultraembedded / core_audio

  View on GitHub
  Audio controller (I2S, SPDIF, DAC)
  ☆101Sep 1, 2019Updated 6 years ago
• alvaroserdotte / SinCos-Encoder-Interface

  View on GitHub
  STM32 Hiperface Encoder circuit and software
  ☆11Nov 14, 2023Updated 2 years ago
• Deploy on Railway without the complexity - Free Credits Offer • Ad
  Connect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
• ultraembedded / core_mmc

  View on GitHub
  MMC (and derivative standards) host controller
  ☆26Sep 14, 2020Updated 5 years ago
• ultraembedded / fpga_test_soc

  View on GitHub
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆35Mar 21, 2020Updated 6 years ago
• ultraembedded / minispartan6-audio

  View on GitHub
  miniSpartan6+ (Spartan6) FPGA based MP3 Player
  ☆28Sep 2, 2019Updated 6 years ago
• peter-g-wilson / yaesa

  View on GitHub
  Yet Another Environment Sensor Aggregator
  ☆10Mar 10, 2022Updated 4 years ago
• rushxrushx / stm32f4_usbaudio

  View on GitHub
  CHEAPEST USB ASYNC AUDIO USING STM32F401RB
  ☆30Mar 17, 2024Updated 2 years ago
• jevinskie / liteluna

  View on GitHub
  LiteX LUNA USB stack integration
  ☆14Jun 12, 2022Updated 4 years ago
• ultraembedded / core_usb_fs_phy

  View on GitHub
  USB Full Speed PHY
  ☆49May 3, 2020Updated 6 years ago
• www-asics-ws / usb2_dev

  View on GitHub
  USB 2.0 Device IP Core
  ☆75Oct 1, 2017Updated 8 years ago
• lambdaconcept / amaranth-to-litex

  View on GitHub
  Use amaranth-to-litex to simply import Amaranth code into a Litex project.
  ☆15Apr 22, 2024Updated 2 years ago
• AI Agents on DigitalOcean Gradient AI Platform • Ad
  Build production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
• bsdphk / pylt

  View on GitHub
  Python LabTools for talking to GPIB instruments
  ☆27Feb 8, 2018Updated 8 years ago
• area / wiiu-gc-adapter-osx

  View on GitHub
  KEXT for allowing the WiiU Gamecube controller adapter to be used in OSX
  ☆11Mar 14, 2015Updated 11 years ago
• davemuscle / sigma_delta_converters

  View on GitHub
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆87Apr 11, 2022Updated 4 years ago
• arpitp / ssd-controller

  View on GitHub
  Open Source SSD Controller. NVMe and Lightstor variants
  ☆17May 21, 2014Updated 12 years ago
• MatejGomboc / Verilog-I2S-Transciever

  View on GitHub
  I2S transciever implemented in Verilog HDL
  ☆33Oct 11, 2017Updated 8 years ago
• ultraembedded / core_enet

  View on GitHub
  Ethernet MAC 10/100 Mbps
  ☆39Oct 31, 2021Updated 4 years ago
• ultraembedded / core_ram_tester

  View on GitHub
  AXI-4 RAM Tester Component
  ☆21Aug 5, 2020Updated 6 years ago