ultraembedded / core_usb_uartLinks
USB serial device (CDC-ACM)
☆40Updated 5 years ago
Alternatives and similar repositories for core_usb_uart
Users that are interested in core_usb_uart are comparing it to the libraries listed below
Sorting:
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆93Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆44Updated 3 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- Audio controller (I2S, SPDIF, DAC)☆88Updated 6 years ago
- Xilinx virtual cable server for generic FTDI 4232H.☆59Updated last year
- SDIO Device Verilog Core☆22Updated 7 years ago
- ULPI Link Wrapper (USB Phy Interface)☆29Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆95Updated 5 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 7 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆62Updated 6 years ago
- FT2232HL JTAG & UART Downloader☆19Updated 4 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- Nitro USB FPGA core☆87Updated last year
- Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com☆109Updated last year
- MIPI DSI transmitter core for Xilinx FPGAs (work in progress)☆84Updated 8 years ago
- Wishbone controlled I2C controllers☆52Updated 10 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆44Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Digilent JTAG clone hardware + eeprom firmware (.bin)☆66Updated 3 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆61Updated 4 years ago
- Xilinx Virtual Cable Server for Raspberry Pi☆115Updated 3 years ago