Alternatives and similar repositories for core_mmc

Users that are interested in core_mmc are comparing it to the libraries listed below

• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆28Updated 3 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 7 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆41Updated 5 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆46Updated 5 years ago
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆16Updated 6 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆37Updated 6 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆45Updated 4 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆23Updated 11 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 9 months ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆16Updated last year
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 9 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆93Updated 5 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆21Updated last week
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 7 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆80Updated 4 years ago
• watz0n / arty_xjtag
  Xilinx JTAG Toolchain on Digilent Arty board
  ☆17Updated 7 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆70Updated 8 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• briansune / USB-PD-3.1-Verilog
  USB-PD-3.1-Verilog
  ☆16Updated last year
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated 3 months ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆30Updated 5 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆37Updated last week
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆21Updated 2 years ago