ultraembedded / core_mmcLinks
MMC (and derivative standards) host controller
☆24Updated 5 years ago
Alternatives and similar repositories for core_mmc
Users that are interested in core_mmc are comparing it to the libraries listed below
Sorting:
- Ethernet MAC 10/100 Mbps☆28Updated 3 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- ☆30Updated 8 years ago
- SDIO Device Verilog Core☆22Updated 7 years ago
- USB serial device (CDC-ACM)☆41Updated 5 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆16Updated 6 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 4 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 9 months ago
- Universal Advanced JTAG Debug Interface☆16Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆93Updated 5 years ago
- Testbenches for HDL projects☆21Updated last week
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Updated 7 years ago
- USB 2.0 Device IP Core☆70Updated 8 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- USB-PD-3.1-Verilog☆16Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated 3 months ago
- ULPI Link Wrapper (USB Phy Interface)☆30Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆21Updated 2 years ago