zhouqinghua / zqh_riscvLinks
zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this project Now it's focusing on Embedded system
☆39Updated 4 years ago
Alternatives and similar repositories for zqh_riscv
Users that are interested in zqh_riscv are comparing it to the libraries listed below
Sorting:
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆32Updated 5 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Updated 3 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Updated 5 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- systemc建模相关☆27Updated 11 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- ☆37Updated 7 years ago
- ☆30Updated 9 months ago
- DDR4 Simulation Project in System Verilog☆43Updated 11 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- DMA Hardware Description with Verilog☆18Updated 6 years ago
- ☆16Updated 6 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆72Updated 6 years ago
- ☆38Updated 10 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- ☆33Updated 4 years ago
- ☆22Updated 6 years ago
- ☆20Updated 3 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year