zhouqinghua / zqh_riscvLinks
zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this project Now it's focusing on Embedded system
☆38Updated 4 years ago
Alternatives and similar repositories for zqh_riscv
Users that are interested in zqh_riscv are comparing it to the libraries listed below
Sorting:
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- ☆38Updated 10 years ago
- Implementation of the PCIe physical layer☆50Updated 3 months ago
- systemc建模相关☆27Updated 11 years ago
- OpenXuantie - OpenE902 Core☆157Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- DMA Hardware Description with Verilog☆17Updated 5 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812 ,Flash)☆21Updated 2 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆112Updated 3 years ago
- ☆16Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- ☆79Updated 3 years ago
- ☆37Updated 6 years ago
- soc integration script and integration smoke script☆24Updated 3 years ago
- AXI Interconnect☆53Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- ☆31Updated 4 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- ARM中通过APB总线连接的UART模块☆68Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago