ultraembedded / cores
Various HDL (Verilog) IP Cores
☆786Updated 3 years ago
Alternatives and similar repositories for cores
Users that are interested in cores are comparing it to the libraries listed below
Sorting:
- Verilog I2C interface for FPGA implementation☆606Updated 2 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆454Updated 3 years ago
- Verilog UART☆480Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,272Updated last week
- Verilog AXI stream components for FPGA implementation☆802Updated 2 months ago
- Verilog AXI components for FPGA implementation☆1,713Updated 2 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆335Updated last year
- Verilog PCI express components☆1,289Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆573Updated 7 years ago
- Bus bridges and other odds and ends☆555Updated last month
- Common SystemVerilog components☆618Updated last week
- SPI Master for FPGA - VHDL and Verilog☆287Updated last year
- Verilog library for ASIC and FPGA designers☆1,282Updated last year
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆481Updated 2 years ago
- ☆615Updated 10 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,065Updated 3 months ago
- Verilog SDRAM memory controller☆328Updated 8 years ago
- 32-bit Superscalar RISC-V CPU☆1,014Updated 3 years ago
- The RIFFA development repository☆828Updated 11 months ago
- synthesiseable ieee 754 floating point library in verilog☆633Updated 2 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆268Updated 4 years ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆579Updated 4 years ago
- VeeR EH1 core☆875Updated last year
- SystemVerilog to Verilog conversion☆627Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆914Updated 6 months ago
- A huge VHDL library for FPGA and digital ASIC development☆382Updated this week
- A full-speed device-side USB peripheral core written in Verilog.☆231Updated 2 years ago
- lowRISC Style Guides☆425Updated 8 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆533Updated last week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆652Updated 6 months ago