Various HDL (Verilog) IP Cores
☆895Jul 1, 2021Updated 4 years ago
Alternatives and similar repositories for cores
Users that are interested in cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆589Oct 10, 2021Updated 4 years ago
- Verilog AXI components for FPGA implementation☆2,030Feb 27, 2025Updated last year
- Verilog library for ASIC and FPGA designers☆1,410May 8, 2024Updated last year
- Verilog Ethernet components for FPGA implementation☆2,947Feb 27, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HDL libraries and projects☆1,905Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,561Apr 22, 2026Updated last week
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆619Mar 15, 2018Updated 8 years ago
- RISC-V CPU Core (RV32IM)☆1,712Sep 18, 2021Updated 4 years ago
- Verilog UART☆552Feb 27, 2025Updated last year
- Bus bridges and other odds and ends☆662Mar 10, 2026Updated last month
- Verilog PCI express components☆1,591Apr 26, 2024Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆89May 15, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog I2C interface for FPGA implementation☆698Feb 27, 2025Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆238Oct 30, 2022Updated 3 years ago
- AMBA bus lecture material☆531Jan 21, 2020Updated 6 years ago
- Basic RISC-V Test SoC☆189Apr 7, 2019Updated 7 years ago
- A simple, basic, formally verified UART controller☆336Jan 29, 2024Updated 2 years ago
- A small, light weight, RISC CPU soft core☆1,531Dec 8, 2025Updated 4 months ago
- Verilog AXI stream components for FPGA implementation☆886Feb 27, 2025Updated last year
- An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA comm…☆879Dec 6, 2024Updated last year
- Common SystemVerilog components☆738Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,121Jun 27, 2024Updated last year
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,541Updated this week
- Audio controller (I2S, SPDIF, DAC)☆97Sep 1, 2019Updated 6 years ago
- Verilog SDRAM memory controller☆367May 13, 2017Updated 8 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,133Feb 11, 2026Updated 2 months ago
- Verilog digital signal processing components☆176Oct 30, 2022Updated 3 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆85Aug 9, 2020Updated 5 years ago
- USB3 PIPE interface for Xilinx 7-Series☆255Apr 3, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Basic USB 1.1 Host Controller for small FPGAs☆99Jun 6, 2020Updated 5 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆594Jan 18, 2023Updated 3 years ago
- SERV - The SErial RISC-V CPU☆1,791Feb 19, 2026Updated 2 months ago
- High Speed USB 2.0 capture device based on miniSpartan6+☆60May 26, 2020Updated 5 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆448Feb 13, 2026Updated 2 months ago
- SPI Slave for FPGA in Verilog and VHDL☆231May 11, 2024Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago