Various HDL (Verilog) IP Cores
☆915Jul 1, 2021Updated 5 years ago
Alternatives and similar repositories for cores
Users that are interested in cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Must-have verilog systemverilog modules☆1,983Mar 12, 2026Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,266Sep 18, 2021Updated 4 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆605Oct 10, 2021Updated 4 years ago
- Verilog AXI components for FPGA implementation☆2,078Feb 27, 2025Updated last year
- Verilog library for ASIC and FPGA designers☆1,429May 8, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog Ethernet components for FPGA implementation☆3,008Feb 27, 2025Updated last year
- HDL libraries and projects☆1,952Jun 25, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,607Updated this week
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆625Mar 15, 2018Updated 8 years ago
- RISC-V CPU Core (RV32IM)☆1,743Sep 18, 2021Updated 4 years ago
- Verilog UART☆573Feb 27, 2025Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 6 years ago
- Bus bridges and other odds and ends☆683Jun 2, 2026Updated last month
- Verilog PCI express components☆1,615Apr 26, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Basic USB-CDC device core (Verilog)☆91May 15, 2021Updated 5 years ago
- Verilog I2C interface for FPGA implementation☆705Feb 27, 2025Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆241Oct 30, 2022Updated 3 years ago
- AMBA bus lecture material☆538Jan 21, 2020Updated 6 years ago
- Basic RISC-V Test SoC☆199Apr 7, 2019Updated 7 years ago
- A simple, basic, formally verified UART controller☆342Jan 29, 2024Updated 2 years ago
- A small, light weight, RISC CPU soft core☆1,559Dec 8, 2025Updated 6 months ago
- Verilog AXI stream components for FPGA implementation☆898Feb 27, 2025Updated last year
- An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA comm…☆906Dec 6, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Common SystemVerilog components☆762Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,233Jun 27, 2024Updated 2 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,579May 12, 2026Updated last month
- Audio controller (I2S, SPDIF, DAC)☆99Sep 1, 2019Updated 6 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,177Feb 11, 2026Updated 4 months ago
- Verilog SDRAM memory controller☆373May 13, 2017Updated 9 years ago
- Verilog digital signal processing components☆184Oct 30, 2022Updated 3 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆86Aug 9, 2020Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- USB3 PIPE interface for Xilinx 7-Series☆266Apr 3, 2026Updated 2 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆100Jun 6, 2020Updated 6 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆611Jan 18, 2023Updated 3 years ago
- SERV - The SErial RISC-V CPU☆1,822Jun 17, 2026Updated 2 weeks ago
- High Speed USB 2.0 capture device based on miniSpartan6+☆60May 26, 2020Updated 6 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆462Feb 13, 2026Updated 4 months ago
- SPI Slave for FPGA in Verilog and VHDL☆232May 11, 2024Updated 2 years ago