habibagamal / SoC_Automation
SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
☆36Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for SoC_Automation
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆15Updated 6 months ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- ☆39Updated 2 years ago
- SRAM☆20Updated 4 years ago
- YosysHQ SVA AXI Properties☆32Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- ☆10Updated 4 months ago
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- ☆22Updated 8 months ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- APB UVC ported to Verilator☆11Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆23Updated 5 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated 3 weeks ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- CORE-V MCU UVM Environment and Test Bench☆17Updated 4 months ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- SystemVerilog Linter based on pyslang☆23Updated 8 months ago
- ☆20Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆29Updated 3 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago