habibagamal / SoC_AutomationLinks
SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
☆39Updated 4 years ago
Alternatives and similar repositories for SoC_Automation
Users that are interested in SoC_Automation are comparing it to the libraries listed below
Sorting:
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- ☆43Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated last month
- Verilog HDL implementation of SDRAM controller and SDRAM model☆30Updated last year
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- SystemVerilog FSM generator☆32Updated last year
- General Purpose AXI Direct Memory Access☆59Updated last year
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- SRAM☆22Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- ☆21Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆32Updated 4 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- Platform Level Interrupt Controller☆43Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆39Updated 3 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 5 months ago
- ☆13Updated last year
- Contains commonly used UVM components (agents, environments and tests).☆30Updated 7 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated 2 years ago