habibagamal / SoC_AutomationLinks
SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
☆39Updated 5 years ago
Alternatives and similar repositories for SoC_Automation
Users that are interested in SoC_Automation are comparing it to the libraries listed below
Sorting:
- Python Tool for UVM Testbench Generation☆55Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated last week
- ☆22Updated 5 years ago
- ☆41Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆16Updated 2 weeks ago
- An open source, parameterized SystemVerilog digital hardware IP library☆32Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆58Updated 6 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆28Updated 3 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- APB Logic☆23Updated last week
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Updated 7 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Updated 3 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- ☆20Updated 11 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- Open Source PHY v2☆33Updated last year
- SRAM☆22Updated 5 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago