habibagamal / SoC_Automation
SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
☆38Updated 4 years ago
Alternatives and similar repositories for SoC_Automation:
Users that are interested in SoC_Automation are comparing it to the libraries listed below
- ☆40Updated 3 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- SRAM☆21Updated 4 years ago
- ☆19Updated 5 years ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- APB UVC ported to Verilator☆11Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated last year
- Common SystemVerilog RTL modules for RgGen☆12Updated last month
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆25Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 10 months ago
- ☆31Updated 2 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆55Updated 2 years ago
- SystemVerilog Linter based on pyslang☆29Updated 2 months ago
- Various low power labs using sky130☆12Updated 3 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last week
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆38Updated 3 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆53Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- SoC Based on ARM Cortex-M3☆29Updated 3 weeks ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago