habibagamal / SoC_AutomationLinks
SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
☆39Updated 4 years ago
Alternatives and similar repositories for SoC_Automation
Users that are interested in SoC_Automation are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- Python Tool for UVM Testbench Generation☆53Updated last year
- ☆42Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- SRAM☆22Updated 4 years ago
- ☆21Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆28Updated last year
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- Import and export IP-XACT XML register models☆35Updated 2 months ago
- ☆35Updated 2 months ago
- Platform Level Interrupt Controller☆41Updated last year
- Open Source PHY v2☆29Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆33Updated 3 months ago
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- Contains commonly used UVM components (agents, environments and tests).☆29Updated 7 years ago
- ☆30Updated this week
- General Purpose AXI Direct Memory Access☆57Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆63Updated 2 weeks ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- ☆20Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated last year