SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
☆39Dec 4, 2020Updated 5 years ago
Alternatives and similar repositories for SoC_Automation
Users that are interested in SoC_Automation are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆18Oct 6, 2025Updated 5 months ago
- NucleusRV (rv32-imafc) - A 32-bit 5 staged pipelined risc-v core.☆78Feb 25, 2026Updated last month
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Jan 15, 2026Updated 2 months ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- Notebooks for Hardware-Aware Training of Spiking Neural Networks. Open-Source Neuromorphic Circuit Design Tutorial at ESSCIRC 2023.☆26Sep 11, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- USB Full Speed PHY☆49May 3, 2020Updated 5 years ago
- 给定ARM Cortex-M3的软核，扩展周围的AMBA总线以及基本外设，完成在上面的汇编以及C语言的执行☆19Aug 26, 2019Updated 6 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆34May 28, 2021Updated 4 years ago
- Arm Cortex-M0 based Customizable SoC for IoT Applications☆16Nov 4, 2020Updated 5 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- RISC-V vector extension ISA simulation☆17Jun 11, 2019Updated 6 years ago
- Mathematical Functions in Verilog☆97Mar 7, 2021Updated 5 years ago
- ☆21Jun 17, 2014Updated 11 years ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- https://ve0x10.in/idf-notes-sra/☆13May 27, 2020Updated 5 years ago
- Student starter code for Fall 2019 labs☆13Nov 28, 2019Updated 6 years ago
- Converts GDSII files to STL files.☆42Dec 12, 2023Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Mar 23, 2026Updated last week
- Simulations and designs for bit serial ALU implemented in TTL circuitry. Also bit serial cpu architectures - all simulated using H. Neem…☆12Aug 26, 2022Updated 3 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated 11 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆51Mar 21, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 6 years ago
- IOPMP IP☆24Jul 11, 2025Updated 8 months ago
- ☆27Feb 15, 2025Updated last year
- Fusesoc compatible rtl cores☆17Nov 23, 2022Updated 3 years ago
- ideas and eda software for vlsi design☆51Mar 20, 2026Updated last week
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 6 years ago
- Implementation of the PCIe physical layer☆62Jul 11, 2025Updated 8 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆34Jun 5, 2024Updated last year
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆140May 14, 2021Updated 4 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆35Mar 23, 2026Updated last week
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Jun 22, 2024Updated last year
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- A repo of basic Verilog/SystemVerilog modules useful in other circuits.☆21Nov 18, 2017Updated 8 years ago
- An open-source custom cache generator.☆35Mar 14, 2024Updated 2 years ago