Verdvana / Async_FIFOLinks
位宽和深度可定制的异步FIFO
☆13Updated last year
Alternatives and similar repositories for Async_FIFO
Users that are interested in Async_FIFO are comparing it to the libraries listed below
Sorting:
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆13Updated 5 years ago
- ☆19Updated 2 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- ☆25Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- ☆14Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆20Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- ☆16Updated 6 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- Example of a full DC synthesis script for a simple design☆10Updated 6 years ago
- ☆12Updated 9 years ago
- Design and UVM-TB of RISC -V Microprocessor☆20Updated 11 months ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆10Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- Simple demo showing how to use the ping pong FIFO☆14Updated 9 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- AXI4 with a FIFO integrated with VIP☆19Updated last year
- ☆20Updated 2 years ago
- 基于FPGA的FFT☆17Updated 6 years ago
- ☆14Updated 5 years ago
- Verification IP for UART protocol☆17Updated 4 years ago
- UVM Testbench for synchronus fifo☆17Updated 4 years ago