openasic-org / xk265
xk265:HEVC/H.265 Video Encoder IP Core (RTL)
☆241Updated last year
Alternatives and similar repositories for xk265:
Users that are interested in xk265 are comparing it to the libraries listed below
- H264视频解码verilog实现☆79Updated 7 years ago
- H265 decoder write in verilog, verified on Xilinx ZYNQ7035☆70Updated 3 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆121Updated last year
- image processing based FPGA☆102Updated 3 years ago
- Vivado诸多IP,包括图像处理等☆198Updated 7 months ago
- High throughput JPEG decoder in Verilog for FPGA☆222Updated 3 years ago
- xk264:AVC/H.264 Video Encoder IP Core (RTL)☆33Updated 2 years ago
- 基于verilog实现了ISP图像处理IP☆252Updated 2 years ago
- xkISP:Xinkai ISP IP Core (HLS)☆271Updated 2 years ago
- ☆130Updated 9 years ago
- CNN accelerator implemented with Spinal HDL☆146Updated last year
- JPEG Encoder Verilog☆74Updated 2 years ago
- FPGA☆122Updated 4 years ago
- ISP-Lite, VIP, MIPI-RX IP实现,测试平台为KV260+AR1335 3MP@30fps☆92Updated 2 years ago
- ☆141Updated 4 years ago
- ☆89Updated 8 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 9 months ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆85Updated 7 years ago
- 基于Xilinx Zynq 嵌入式软硬件协同设计实战指南☆83Updated 9 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆331Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆114Updated 2 years ago
- ☆23Updated 4 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆240Updated 6 months ago
- AXI Interface Nand Flash Controller (Sync mode)☆91Updated 7 months ago
- 视频旋转(2019FPGA大赛)☆33Updated 4 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆171Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆194Updated last year
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆236Updated 3 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆170Updated last year
- OpenXuantie - OpenE906 Core☆138Updated 8 months ago