openasic-org / xk265Links
xk265:HEVC/H.265 Video Encoder IP Core (RTL)
☆251Updated 2 years ago
Alternatives and similar repositories for xk265
Users that are interested in xk265 are comparing it to the libraries listed below
Sorting:
- H264视频解码verilog实现☆82Updated 7 years ago
- H265 decoder write in verilog, verified on Xilinx ZYNQ7035☆71Updated 3 years ago
- xk264:AVC/H.264 Video Encoder IP Core (RTL)☆39Updated 2 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆129Updated last year
- ISP-Lite, VIP, MIPI-RX IP实现,测试平台为KV260+AR1335 3MP@30fps☆98Updated 2 years ago
- ☆136Updated 10 years ago
- High throughput JPEG decoder in Verilog for FPGA☆233Updated 3 years ago
- image processing based FPGA☆109Updated 3 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆92Updated 7 years ago
- 基于Xilinx Zynq 嵌入式软硬件协 同设计实战指南☆83Updated 9 years ago
- Vivado诸多IP,包括图像处理等☆209Updated 11 months ago
- JPEG Encoder Verilog☆76Updated 2 years ago
- 视频旋转(2019FPGA大赛)☆34Updated 5 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆121Updated 2 years ago
- 基于verilog实现了ISP图像处理IP☆277Updated 2 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆35Updated 7 years ago
- ☆142Updated 4 years ago
- FPGA☆125Updated 5 years ago
- OpenXuantie - OpenE902 Core☆152Updated last year
- Cortex M0 based SoC☆73Updated 3 years ago
- xkISP:Xinkai ISP IP Core (HLS)☆284Updated 2 years ago
- Example designs for FPGA Drive FMC☆256Updated 6 months ago
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- 基于verilog实现了ISP图像处理IP(Altera EP4CE6)☆21Updated 3 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆131Updated last year
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆346Updated last year
- AXI协议规范中文翻译版☆153Updated 3 years ago
- 国产VU13P加速卡资料☆73Updated 4 months ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆249Updated 6 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated last year