openasic-org / xk265Links
xk265:HEVC/H.265 Video Encoder IP Core (RTL)
☆266Updated 2 years ago
Alternatives and similar repositories for xk265
Users that are interested in xk265 are comparing it to the libraries listed below
Sorting:
- H264视频解码verilog实现☆85Updated 8 years ago
- H265 decoder write in verilog, verified on Xilinx ZYNQ7035☆80Updated 4 years ago
- xk264:AVC/H.264 Video Encoder IP Core (RTL)☆50Updated 2 years ago
- ☆143Updated 10 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆142Updated last year
- image processing based FPGA☆115Updated 4 years ago
- JPEG Encoder Verilog☆79Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- High throughput JPEG decoder in Verilog for FPGA☆252Updated 3 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表 图像采集及存储系统☆96Updated 8 years ago
- Vivado诸多IP,包括图像处理等☆234Updated last year
- ☆144Updated 5 years ago
- ISP-Lite, VIP, MIPI-RX IP实现,测试平台为KV260+AR1335 3MP@30fps☆106Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆156Updated last year
- 视频旋转(2019FPGA大赛)☆37Updated 5 years ago
- A Synthesizable implementation of H.264 Video Decoding☆33Updated 9 years ago
- 基于Xilinx Zynq 嵌入式软硬件协同设计实战指南☆86Updated 10 years ago
- Pynq computer vision examples with an OV5640 camera☆58Updated 5 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆377Updated 2 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Updated 4 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆301Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆211Updated 2 years ago
- OpenXuantie - OpenE902 Core☆166Updated last year
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆283Updated 7 years ago
- FPGA☆126Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆147Updated last year
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆147Updated 2 years ago
- ☆24Updated 4 years ago
- Example designs for FPGA Drive FMC☆284Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago