fengyulin1996 / Verilog-DSPView external linksLinks
FIR，FFT based on Verilog
☆14Dec 3, 2017Updated 8 years ago
Alternatives and similar repositories for Verilog-DSP
Users that are interested in Verilog-DSP are comparing it to the libraries listed below
Sorting:
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 6 years ago
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32May 6, 2017Updated 8 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆48Oct 21, 2016Updated 9 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- FFT implement by verilog_测试验证已通过☆61Sep 14, 2016Updated 9 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Oct 16, 2017Updated 8 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- 位宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- ☆14Feb 24, 2025Updated 11 months ago
- Direct Access Memory for MPSoC☆13Jan 27, 2026Updated 3 weeks ago
- hdmi-ts Project☆13Jun 11, 2017Updated 8 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 11 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆33Aug 7, 2021Updated 4 years ago
- Design real-time image processing, object recognition and PID control for Autonomous Drone.☆35Nov 26, 2017Updated 8 years ago
- RTL Verilog library for various DSP modules☆94Feb 17, 2022Updated 4 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 12 years ago
- IIR Lowpass Filter☆13Jan 12, 2018Updated 8 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago