fengyulin1996 / Verilog-DSP
FIR,FFT based on Verilog
☆13Updated 7 years ago
Alternatives and similar repositories for Verilog-DSP:
Users that are interested in Verilog-DSP are comparing it to the libraries listed below
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Updated 9 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- ☆16Updated 5 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- FIR band-pass filter using Verilog HDL.☆11Updated 4 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- 位宽和深度可定制的异步FIFO☆13Updated 10 months ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- minimal code to access ps DDR from PL☆19Updated 5 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- ☆19Updated 4 years ago
- UVM testbench for verifying the Pulpino SoC☆13Updated 5 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Updated 6 years ago
- DDR3 function verification environment in UVM☆23Updated 7 years ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- FIR implemention with Verilog☆46Updated 5 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆14Updated 2 months ago
- Verification of Ethernet Switch System Verilog☆11Updated 8 years ago
- 基于FPGA的FFT☆12Updated 6 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆23Updated last year
- Simple demo showing how to use the ping pong FIFO☆14Updated 8 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆14Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago