tomverbeure / intel_jtag_primitive_blog
How to use the Intel JTAG primitive without using virtual JTAG
☆16Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for intel_jtag_primitive_blog
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- Use ECP5 JTAG port to interact with user design☆24Updated 3 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆17Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated last year
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆36Updated 6 months ago
- VexRiscV system with GDB-Server in Hardware☆20Updated last year
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆23Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 5 years ago
- Side channel communication test within an FPGA☆11Updated 4 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- PLEASE MOVE TO PAWSv2☆17Updated 2 years ago
- Bit streams forthe Ulx3s ECP5 device☆16Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Mini CPU design with JTAG UART support☆18Updated 3 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆14Updated 2 years ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- An FPGA/PCI Device Reference Platform☆28Updated 3 years ago
- Test of a RP2040 PMOD attached to a LiteX SoC.☆24Updated last year
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- ☆14Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Programmable multichannel ADPCM decoder for FPGA☆23Updated 3 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 3 years ago
- A SoC for DOOM☆16Updated 3 years ago
- ☆36Updated 2 years ago