ultraembedded / core_usb_bridgeLinks
USB -> AXI Debug Bridge
☆39Updated 4 years ago
Alternatives and similar repositories for core_usb_bridge
Users that are interested in core_usb_bridge are comparing it to the libraries listed below
Sorting:
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 9 months ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- ☆25Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- UART models for cocotb☆29Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆26Updated last week
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- Basic Verilog Ethernet core and C driver functions☆11Updated 3 months ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆82Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Implementation of the PCIe physical layer☆40Updated 3 weeks ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 4 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago