Alternatives and similar repositories for core_usb_bridge

Users that are interested in core_usb_bridge are comparing it to the libraries listed below

• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 5 months ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆22Updated 7 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆64Updated 5 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆27Updated 3 weeks ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 5 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆33Updated 5 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 4 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆27Updated 6 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆34Updated 4 years ago
• GOOD-Stuff / FPGA-SPI-Flash
  Various projects of SPI loader module for xilinx fpga
  ☆31Updated 4 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆57Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆39Updated 3 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆55Updated 5 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆18Updated 11 months ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago