ultraembedded / core_usb_bridgeLinks
USB -> AXI Debug Bridge
☆39Updated 4 years ago
Alternatives and similar repositories for core_usb_bridge
Users that are interested in core_usb_bridge are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆63Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 4 months ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 7 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- ☆16Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 5 months ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- ☆21Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago