ultraembedded / core_usb_bridgeLinks
USB -> AXI Debug Bridge
☆39Updated 4 years ago
Alternatives and similar repositories for core_usb_bridge
Users that are interested in core_usb_bridge are comparing it to the libraries listed below
Sorting:
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- ☆26Updated 4 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆28Updated this week
- ☆14Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Generic AXI master stub☆19Updated 10 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆16Updated 4 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆72Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆31Updated last month
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 5 months ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- JTAG Test Access Port (TAP)☆34Updated 10 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- UART models for cocotb☆29Updated 2 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago