freecores / usb_phyLinks
USB 1.1 PHY
☆11Updated 11 years ago
Alternatives and similar repositories for usb_phy
Users that are interested in usb_phy are comparing it to the libraries listed below
Sorting:
- USB Full Speed PHY☆46Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- turbo 8051☆29Updated 8 years ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Testbenches for HDL projects☆20Updated this week
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- AES☆14Updated 2 years ago
- ☆16Updated 6 years ago
- Cortex-M0 DesignStart Wrapper☆20Updated 6 years ago
- ☆30Updated 8 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- USB1.1 Host Controller + PHY☆14Updated 4 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 8 months ago
- SDIO Device Verilog Core☆22Updated 7 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 7 months ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Updated 11 years ago
- QSPI for SoC☆22Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- ☆14Updated 7 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- Xilinx IP repository☆13Updated 7 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago