shalan / QSPI_XIP_CTRL_DMCView external linksLinks
Quad SPI Flash XIP Controller with a direct mapped cache
☆12Dec 9, 2020Updated 5 years ago
Alternatives and similar repositories for QSPI_XIP_CTRL_DMC
Users that are interested in QSPI_XIP_CTRL_DMC are comparing it to the libraries listed below
Sorting:
- QSPI for SoC☆23Nov 8, 2019Updated 6 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 位宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year
- ☆12Nov 11, 2015Updated 10 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆31Oct 31, 2021Updated 4 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- ☆14Feb 24, 2025Updated 11 months ago
- Direct Access Memory for MPSoC☆13Jan 27, 2026Updated 2 weeks ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- USB1.1 Host Controller + PHY☆15Aug 4, 2021Updated 4 years ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆15Nov 9, 2023Updated 2 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 11 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Apr 15, 2020Updated 5 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- ☆18Aug 11, 2022Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆16Jun 24, 2020Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- OV7670 (Verilog HDL)Drive for FPGA☆18Mar 4, 2019Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 5 years ago