shalan / QSPI_XIP_CTRL_DMC

Related projects: ⓘ

• open-dv / dma_axi
  ☆16Updated 5 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆17Updated 4 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆9Updated 5 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 2 years ago
• caicaicai-ji / QSPI_FOR_SOC
  QSPI for SoC
  ☆15Updated 4 years ago
• WajahatRiaz / AHB-Lite-Protocol-Verification
  ☆19Updated this week
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆15Updated 4 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆18Updated 10 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆16Updated 5 years ago
• Milo-F / PCIe_AXI
  PCIe Memory R/W TLP与AXI总线桥
  ☆15Updated 2 years ago
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆20Updated 6 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆16Updated 10 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆15Updated 5 years ago
• wanderingnail / AXI_DMA
  ☆14Updated last year
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆13Updated 10 years ago
• zhouzaixin / arm_soc
  ☆13Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆19Updated 4 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆20Updated 4 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆20Updated 4 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 6 years ago
• redchenjs / wujian100_open
  平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）
  ☆14Updated last year
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆24Updated 3 years ago
• rbarzic / ml-ahb-gen
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆12Updated 7 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆10Updated 8 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆28Updated 4 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆15Updated 4 years ago
• bohanw / jpeg_comp_verilog
  JPEG Compression RTL implementation
  ☆9Updated 7 years ago