Alternatives and similar repositories for QSPI_XIP_CTRL_DMC:

Users that are interested in QSPI_XIP_CTRL_DMC are comparing it to the libraries listed below

• open-dv / dma_axi
  ☆16Updated 5 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 5 years ago
• caicaicai-ji / QSPI_FOR_SOC
  QSPI for SoC
  ☆22Updated 5 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆21Updated 7 years ago
• zhouzaixin / arm_soc
  ☆14Updated 5 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆18Updated 5 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆16Updated 5 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆21Updated 10 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 7 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆25Updated 6 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 6 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆16Updated 4 years ago
• AdriaanSwan / Verilog-I2C-Slave
  Verilog I2C Slave
  ☆23Updated 10 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆31Updated 5 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆25Updated 3 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 9 years ago
• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated 9 months ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 6 years ago