yigitbektasgursoy / SDRAM_VerilogLinks
Verilog HDL implementation of SDRAM controller and SDRAM model
☆29Updated last year
Alternatives and similar repositories for SDRAM_Verilog
Users that are interested in SDRAM_Verilog are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- RISC-V Nox core☆68Updated last month
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 7 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- UART -> AXI Bridge☆63Updated 4 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆60Updated 4 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆58Updated 5 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- DMA Hardware Description with Verilog☆15Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- SPI-Flash XIP Interface (Verilog)☆43Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago