Verilog HDL implementation of SDRAM controller and SDRAM model
☆51Jun 19, 2024Updated 2 years ago
Alternatives and similar repositories for SDRAM_Verilog
Users that are interested in SDRAM_Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog SDRAM memory controller☆388May 13, 2017Updated 9 years ago
- Motion Estimation implementation by using Verilog HDL☆14Jun 17, 2024Updated 2 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆87Sep 7, 2020Updated 6 years ago
- Basic RISC-V Test SoC☆212Apr 7, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Repository containing ULX3S blink LED binaries☆16May 16, 2022Updated 4 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆642Oct 10, 2021Updated 5 years ago
- Zucker SOC☆17Jun 11, 2025Updated last year
- Opensource DDR3 Controller☆497Sep 12, 2026Updated last month
- ☆14Nov 5, 2017Updated 8 years ago
- Single-Cycle RISC-V Processor in systemverylog☆28Apr 23, 2019Updated 7 years ago
- This repository contains C++ implementation of A* search algorithm for finding path to goal state for 8 puzzle problem in AI.☆11Dec 2, 2023Updated 2 years ago
- Octave/MATLAB code for generating compensation FIR coefficients☆14Sep 7, 2015Updated 11 years ago
- ☆22May 8, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- This is a detailed SystemVerilog course☆172Mar 4, 2025Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆102Aug 20, 2026Updated 2 months ago
- Firmware / software / Verilog for the Photon camera☆18Oct 8, 2026Updated 3 weeks ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆20Jun 24, 2021Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- ☆13May 8, 2022Updated 4 years ago
- Verilog UART☆204Jun 4, 2013Updated 13 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆26Jan 10, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Single Cycle CPU using the RV32I Base Instruction set☆25Nov 5, 2025Updated 11 months ago
- RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card☆29Oct 15, 2026Updated 2 weeks ago
- Basic USB 1.1 Host Controller for small FPGAs☆103Jun 6, 2020Updated 6 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆51Mar 22, 2019Updated 7 years ago
- ☆58Jun 19, 2021Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- ☆36Mar 8, 2023Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆94Apr 8, 2024Updated 2 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆20Dec 8, 2017Updated 8 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆234Jan 29, 2024Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆496Oct 17, 2026Updated last week
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated 2 months ago
- Introductory course into static timing analysis (STA).☆116Jul 6, 2025Updated last year
- Simple 8-bit UART realization on Verilog HDL.☆121Apr 27, 2024Updated 2 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆223Sep 15, 2023Updated 3 years ago
- Structured UVM Course☆77Jan 4, 2024Updated 2 years ago