JulianKemmerer / Drexel-ECEC575Links
☆20Updated 11 years ago
Alternatives and similar repositories for Drexel-ECEC575
Users that are interested in Drexel-ECEC575 are comparing it to the libraries listed below
Sorting:
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- Repository gathering basic modules for CDC purpose☆56Updated 6 years ago
- ☆33Updated last month
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- APB Logic☆22Updated last month
- A Verilog implementation of a processor cache.☆34Updated 8 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated 2 months ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- Open source process design kit for 28nm open process☆72Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆24Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 3 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Common SystemVerilog RTL modules for RgGen☆15Updated 2 weeks ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- SRAM☆22Updated 5 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆33Updated 3 weeks ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆25Updated 4 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆148Updated last week
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Updated 3 weeks ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 3 years ago
- To design test bench of the APB protocol☆18Updated 5 years ago