JulianKemmerer / Drexel-ECEC575
☆19Updated 10 years ago
Alternatives and similar repositories for Drexel-ECEC575:
Users that are interested in Drexel-ECEC575 are comparing it to the libraries listed below
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- ☆21Updated 5 years ago
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- SoC Based on ARM Cortex-M3☆30Updated 2 weeks ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆15Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 6 months ago
- Various low power labs using sky130☆12Updated 3 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- ☆26Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated last year
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 3 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- APB UVC ported to Verilator☆11Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- ☆24Updated last year
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- Open Source PHY v2☆27Updated last year
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago