☆21Jun 17, 2014Updated 11 years ago
Alternatives and similar repositories for Drexel-ECEC575
Users that are interested in Drexel-ECEC575 are comparing it to the libraries listed below
Sorting:
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 5 years ago
- Memory Compiler Tutorial☆14Aug 2, 2022Updated 3 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆17Jan 28, 2022Updated 4 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Mar 28, 2025Updated 11 months ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Sep 21, 2021Updated 4 years ago
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆23Nov 7, 2022Updated 3 years ago
- RISC-V vector extension ISA simulation☆16Jun 11, 2019Updated 6 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Dec 4, 2020Updated 5 years ago
- 基于FPGA的交通灯☆18Dec 21, 2018Updated 7 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 5 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago
- RISC-V instruction set extensions for SM4 block cipher☆21Mar 6, 2020Updated 6 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 7 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- ideas and eda software for vlsi design☆51Feb 6, 2026Updated last month
- Python Model of the RISC-V ISA☆62Jul 23, 2022Updated 3 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- ☆35Dec 10, 2023Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆58Jul 9, 2020Updated 5 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- SRAM build space for SKY130 provided by SkyWater.☆25Oct 20, 2021Updated 4 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆34May 28, 2021Updated 4 years ago
- ☆34Feb 17, 2026Updated 2 weeks ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Jul 25, 2021Updated 4 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Jul 25, 2023Updated 2 years ago