JulianKemmerer / Drexel-ECEC575
☆19Updated 10 years ago
Alternatives and similar repositories for Drexel-ECEC575:
Users that are interested in Drexel-ECEC575 are comparing it to the libraries listed below
- ☆26Updated 5 years ago
- SRAM☆21Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 10 months ago
- ☆40Updated 3 years ago
- APB UVC ported to Verilator☆11Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated last month
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆15Updated 10 months ago
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- ☆23Updated last year
- ☆19Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆76Updated 11 months ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆31Updated 5 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago