USB 2.0 Device IP Core
☆74Oct 1, 2017Updated 8 years ago
Alternatives and similar repositories for usb2_dev
Users that are interested in usb2_dev are comparing it to the libraries listed below
Sorting:
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- USB 1.1 Device IP Core☆21Oct 1, 2017Updated 8 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Dec 2, 2018Updated 7 years ago
- USB 1.1 Host and Function IP core☆25Jul 17, 2014Updated 11 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- USB1.1 Host Controller + PHY☆15Aug 4, 2021Updated 4 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆237Oct 30, 2022Updated 3 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- USB2.0 Device Controller IP Core☆14Aug 18, 2023Updated 2 years ago
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- Basic USB-CDC device core (Verilog)☆87May 15, 2021Updated 4 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 5 months ago
- SDIO Device Verilog Core☆24Jul 25, 2018Updated 7 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆29Aug 16, 2021Updated 4 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 5 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Icarus SIMBUS☆20Nov 6, 2019Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆102Jan 27, 2024Updated 2 years ago
- USB serial device (CDC-ACM)☆45Jun 28, 2020Updated 5 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- ☆18Jul 9, 2025Updated 7 months ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Nov 29, 2024Updated last year
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 7 years ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 7 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago