ultraembedded / core_enetLinks
Ethernet MAC 10/100 Mbps
☆27Updated 3 years ago
Alternatives and similar repositories for core_enet
Users that are interested in core_enet are comparing it to the libraries listed below
Sorting:
- SPI-Flash XIP Interface (Verilog)☆40Updated 3 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆29Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated last year
- Xilinx IP repository☆13Updated 7 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 6 months ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- Cortex-M0 DesignStart Wrapper☆20Updated 5 years ago
- ☆30Updated 8 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- ☆14Updated 7 years ago
- ULPI Link Wrapper (USB Phy Interface)☆28Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- ☆59Updated 3 years ago
- ☆14Updated 2 years ago