ultraembedded / core_enetLinks
Ethernet MAC 10/100 Mbps
☆27Updated 3 years ago
Alternatives and similar repositories for core_enet
Users that are interested in core_enet are comparing it to the libraries listed below
Sorting:
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 9 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 4 months ago
- USB Full Speed PHY☆44Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 3 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- ULPI Link Wrapper (USB Phy Interface)☆27Updated 5 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆12Updated last year
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- Xilinx IP repository☆13Updated 7 years ago
- Imaging application using MIPI and DisplayPort to process image☆23Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆17Updated 2 years ago
- SDIO Device Verilog Core☆22Updated 6 years ago
- turbo 8051☆29Updated 7 years ago
- AXI-4 RAM Tester Component☆17Updated 4 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- ☆30Updated 8 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 4 months ago