ultraembedded / core_enet
Ethernet MAC 10/100 Mbps
☆24Updated 3 years ago
Alternatives and similar repositories for core_enet:
Users that are interested in core_enet are comparing it to the libraries listed below
- AXI-4 RAM Tester Component☆17Updated 4 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- USB 1.1 Host and Function IP core☆20Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆22Updated 5 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- MMC (and derivative standards) host controller☆23Updated 4 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Verilog IP Cores & Tests☆12Updated 6 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 8 months ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆23Updated 3 years ago
- turbo 8051☆28Updated 7 years ago
- Xilinx IP repository☆13Updated 6 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 6 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Updated 4 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆16Updated last year
- Wishbone interconnect utilities☆38Updated 8 months ago
- Control a MIPI Camera over I2C☆21Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- ☆17Updated 4 years ago
- USB capture IP☆20Updated 4 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated last month
- Imaging application using MIPI and DisplayPort to process image☆23Updated 4 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- Verilog Repository for GIT☆31Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆40Updated 4 years ago
- USB serial device (CDC-ACM)☆37Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago