Basic USB 1.1 Host Controller for small FPGAs
☆103Jun 6, 2020Updated 6 years ago
Alternatives and similar repositories for core_usb_host
Users that are interested in core_usb_host are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ULPI Link Wrapper (USB Phy Interface)☆39May 3, 2020Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆87Aug 9, 2020Updated 6 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆37Jul 2, 2023Updated 3 years ago
- Open Source Silicon Development Testing Unit using JTAG☆15Apr 25, 2026Updated 6 months ago
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)☆59Jun 6, 2020Updated 6 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆194Mar 10, 2024Updated 2 years ago
- USB1.1 Host Controller + PHY☆18Aug 4, 2021Updated 5 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆244Oct 30, 2022Updated 4 years ago
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆34Jul 15, 2021Updated 5 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆107Aug 28, 2025Updated last year
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 7 years ago
- Nitro USB FPGA core☆91Mar 1, 2026Updated 8 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆36Oct 15, 2024Updated 2 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆105Feb 17, 2023Updated 3 years ago
- USB3 SuperSpeed (5Gbps) and SuperSpeedPlus (10Gbps) for FPGAs without external chip: PHY + Device Core in LiteX.☆274Updated this week
- Bit streams forthe Ulx3s ECP5 device☆19Apr 9, 2023Updated 3 years ago
- Basic Pong you can extend with rotary, sound, vga generator and autopilot☆11Oct 26, 2021Updated 5 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 4 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆27Apr 24, 2019Updated 7 years ago
- USB 1.1 Host and Function IP core☆27Jul 17, 2014Updated 12 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Basic USB-CDC device core (Verilog)☆95May 15, 2021Updated 5 years ago
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆181Mar 22, 2025Updated last year
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 6 years ago
- EDA Tools: Xilinx ISE 14.7 Dockerfile☆21Jun 20, 2022Updated 4 years ago
- KiCad design for a minimig compatible board for the QM_XC7A100T_DDR3 board.☆24Mar 26, 2023Updated 3 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Apr 22, 2024Updated 2 years ago
- Doom classic port to lightweight RISC‑V☆114Jul 25, 2022Updated 4 years ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 5 years ago
- ☆15May 17, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- DVI video out example for prjtrellis☆17Jan 20, 2019Updated 7 years ago
- Exploring gate level simulation☆60Oct 24, 2026Updated last week
- ☆33Nov 25, 2022Updated 3 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆644Oct 10, 2021Updated 5 years ago
- Code to support porting MiST cores to other boards.☆49Feb 26, 2026Updated 8 months ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated last year