ucb-bar / sha3Links
☆81Updated last year
Alternatives and similar repositories for sha3
Users that are interested in sha3 are comparing it to the libraries listed below
Sorting:
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆77Updated 9 years ago
- A dynamic verification library for Chisel.☆154Updated 8 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Chisel Learning Journey☆109Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆103Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- Pure digital components of a UCIe controller☆66Updated 3 weeks ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- ☆20Updated 5 years ago
- Chisel components for FPGA projects☆126Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- Public release☆57Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆135Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆56Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆171Updated 3 weeks ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆58Updated 2 weeks ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆36Updated 5 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆71Updated last month
- The Task Parallel System Composer (TaPaSCo)☆111Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- ☆33Updated 4 months ago