C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
☆53Jul 14, 2020Updated 5 years ago
Alternatives and similar repositories for rocc-software
Users that are interested in rocc-software are comparing it to the libraries listed below
Sorting:
- Tests for example Rocket Custom Coprocessors☆75Feb 19, 2020Updated 6 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 5 years ago
- ☆80Feb 27, 2024Updated 2 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆22Oct 24, 2020Updated 5 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆62Jun 27, 2025Updated 8 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 5 months ago
- ☆10Nov 8, 2019Updated 6 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 5 months ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated 11 months ago
- ☆13Feb 13, 2021Updated 5 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Dec 16, 2022Updated 3 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.☆12Aug 19, 2018Updated 7 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- ☆87Jan 30, 2026Updated last month
- Using VexRiscv without installing Scala☆39Nov 10, 2021Updated 4 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Oct 2, 2019Updated 6 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Oct 5, 2022Updated 3 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- RISC-V GPGPU☆36Mar 6, 2020Updated 5 years ago
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆244Apr 29, 2024Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- rv8 benchmark suite☆23Jul 30, 2020Updated 5 years ago
- An executable specification of the RISCV ISA in L3.☆42Mar 1, 2019Updated 7 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 5 months ago
- Support for Rocket Chip on Zynq FPGAs☆40Apr 24, 2019Updated 6 years ago
- ☆22Nov 12, 2020Updated 5 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago