IBM / rocc-softwareLinks
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
☆53Updated 5 years ago
Alternatives and similar repositories for rocc-software
Users that are interested in rocc-software are comparing it to the libraries listed below
Sorting:
- ☆80Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- ☆33Updated 7 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆66Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last month
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Useful utilities for BAR projects☆32Updated last year
- ☆20Updated 5 years ago
- ☆50Updated last month
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- ☆80Updated last week