IBM / rocc-softwareLinks
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
☆54Updated 5 years ago
Alternatives and similar repositories for rocc-software
Users that are interested in rocc-software are comparing it to the libraries listed below
Sorting:
- ☆81Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆33Updated 5 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆43Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- ☆20Updated 5 years ago
- Useful utilities for BAR projects☆32Updated last year
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- ☆49Updated 3 months ago
- ☆88Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆48Updated 9 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago