IBM / rocc-softwareLinks
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
☆53Updated 5 years ago
Alternatives and similar repositories for rocc-software
Users that are interested in rocc-software are comparing it to the libraries listed below
Sorting:
- ☆82Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- ☆33Updated 9 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 11 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 7 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- Useful utilities for BAR projects☆32Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 8 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆145Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago