C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
☆53Jul 14, 2020Updated 6 years ago
Alternatives and similar repositories for rocc-software
Users that are interested in rocc-software are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tests for example Rocket Custom Coprocessors☆75Feb 19, 2020Updated 6 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Apr 6, 2020Updated 6 years ago
- ☆81Feb 27, 2024Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆66Jun 27, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆224Jan 23, 2020Updated 6 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆22Oct 24, 2020Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated last year
- A fault-injection framework using Chisel and FIRRTL☆39Sep 17, 2025Updated last year
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Workspace Integration Tool☆23Nov 6, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.☆12Aug 19, 2018Updated 8 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- ☆13Feb 13, 2021Updated 5 years ago
- ☆92Oct 1, 2026Updated last week
- ☆139May 13, 2022Updated 4 years ago
- Using VexRiscv without installing Scala☆40Nov 10, 2021Updated 4 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- ☆42Oct 26, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Oct 2, 2019Updated 7 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- 《关于浮点运算：作为程序员都应该了解什么？》☆28Apr 17, 2018Updated 8 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆250Apr 29, 2024Updated 2 years ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago
- A new memory mapping interface for efficient direct user-space access to byte-addressable storage, published in MICRO2022.☆15Sep 29, 2022Updated 4 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 7 years ago
- Wrapper for Rocket-Chip on FPGAs☆141Oct 5, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Bluespec SystemVerilog library of miscellaneous components☆18Jul 10, 2026Updated 2 months ago
- An executable specification of the RISCV ISA in L3.☆44Mar 1, 2019Updated 7 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- RISC-V GPGPU☆40Mar 6, 2020Updated 6 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆40Jan 26, 2026Updated 8 months ago