freecores / sha3
SHA3 (KECCAK)
☆18Updated 10 years ago
Alternatives and similar repositories for sha3
Users that are interested in sha3 are comparing it to the libraries listed below
Sorting:
- ☆21Updated this week
- ☆13Updated 10 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 9 months ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆37Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 5 months ago
- Platform Level Interrupt Controller☆40Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated last month
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 11 months ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 10 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 6 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- ☆59Updated 3 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆13Updated 6 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 4 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆40Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- PCI bridge☆18Updated 10 years ago
- ☆10Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated this week