freecores / sha3
SHA3 (KECCAK)
☆15Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for sha3
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- RISC-V soft-core PEs for TaPaSCo☆15Updated 5 months ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆12Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- ☆12Updated 9 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆19Updated 6 years ago
- Generic AXI master stub☆19Updated 10 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago
- ☆18Updated 10 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- RISC-V instruction set extensions for SM4 block cipher☆18Updated 4 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆13Updated 2 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- ☆20Updated last week
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Open source FPGA-based NIC and platform for in-network compute☆58Updated last week
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 4 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- VexRiscv reference platforms for the pqriscv project☆15Updated 8 months ago
- SCARV: a side-channel hardened RISC-V platform☆18Updated 3 years ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 10 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Custom Coprocessor Interface for VexRiscv☆10Updated 6 years ago