freecores / sha3
SHA3 (KECCAK)
☆15Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for sha3
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- ☆12Updated 9 years ago
- ☆20Updated last week
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 5 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- ☆25Updated 2 years ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 8 months ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆12Updated 3 years ago
- RISC-V soft-core PEs for TaPaSCo☆15Updated 5 months ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆19Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- DDR3 SDRAM controller☆18Updated 10 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆21Updated last year
- Verilog RTL Design☆24Updated 3 years ago
- APB UVC ported to Verilator☆11Updated last year
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆35Updated 9 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆13Updated 3 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- Generic AXI master stub☆19Updated 10 years ago
- ☆57Updated 3 years ago