Alternatives and similar repositories for midas-examples:

Users that are interested in midas-examples are comparing it to the libraries listed below

• ucb-bar / chisel-awl
  ☆13Updated 4 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• rhit-neuro / deca
  ☆21Updated 4 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆13Updated 3 weeks ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆26Updated 5 years ago
• riscveval / Rocket-Chip
  ☆21Updated 7 years ago
• sequencer / arithmetic
  ☆32Updated 2 weeks ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆28Updated 3 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆17Updated 7 years ago
• sifive / block-nvdla-sifive
  ☆42Updated 3 years ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 4 years ago
• PrincetonUniversity / primesim
  A parallel and distributed simulator for thousand-core chips
  ☆22Updated 6 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆51Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆20Updated 8 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆30Updated 2 years ago
• furkanturan / lowrisc-zed
  LowRISC port to Zedboard
  ☆12Updated 7 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last week
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆28Updated this week
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆15Updated 5 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆20Updated last week
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated last month
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆34Updated last year