ucb-bar / midas-examplesLinks
Simple MIDAS Examples
☆12Updated 7 years ago
Alternatives and similar repositories for midas-examples
Users that are interested in midas-examples are comparing it to the libraries listed below
Sorting:
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Updated 6 years ago
- ☆22Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- ☆13Updated 4 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- ☆81Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Updated 4 years ago
- The home of the Chisel3 website☆21Updated last year
- A prototype GUI for chisel-development☆51Updated 5 years ago
- A vector processor implemented in Chisel☆21Updated 11 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ☆33Updated 8 months ago
- Chisel Learning Journey☆111Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 6 years ago
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- ☆20Updated 5 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆39Updated this week
- A parallel and distributed simulator for thousand-core chips☆26Updated 7 years ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated last month
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 3 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Updated 4 years ago