chick / visualizerLinks
Provides dot visualizations of chisel/firrtl circuites
☆13Updated 6 years ago
Alternatives and similar repositories for visualizer
Users that are interested in visualizer are comparing it to the libraries listed below
Sorting:
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- ☆12Updated 4 years ago
- A vector processor implemented in Chisel☆21Updated 11 years ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- ☆20Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Advanced Debug Interface☆14Updated 9 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆30Updated last month
- Intel Compiler for SystemC☆25Updated 2 years ago
- ☆13Updated 4 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆34Updated this week
- DUTH RISC-V Microprocessor☆22Updated 10 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- A DMA Controller for RISCV CPUs☆13Updated 10 years ago
- A configurable SRAM generator☆56Updated 2 months ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Open source RTL simulation acceleration on commodity hardware☆30Updated 2 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- ☆16Updated 4 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- Chisel Cheatsheet☆34Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆43Updated last week