chick / visualizerLinks
Provides dot visualizations of chisel/firrtl circuites
☆13Updated 6 years ago
Alternatives and similar repositories for visualizer
Users that are interested in visualizer are comparing it to the libraries listed below
Sorting:
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- ☆20Updated 5 years ago
- ☆12Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- Chisel Things for OFDM☆32Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- ☆32Updated last week
- A vector processor implemented in Chisel☆21Updated 11 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- A configurable SRAM generator☆57Updated 3 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- BFM Tester for Chisel HDL☆14Updated 4 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated this week
- Useful utilities for BAR projects☆32Updated last year
- A prototype GUI for chisel-development☆51Updated 5 years ago
- sram/rram/mram.. compiler☆43Updated 2 years ago
- Advanced Debug Interface☆14Updated 10 months ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- ☆13Updated 4 years ago