chick / visualizerLinks
Provides dot visualizations of chisel/firrtl circuites
☆12Updated 6 years ago
Alternatives and similar repositories for visualizer
Users that are interested in visualizer are comparing it to the libraries listed below
Sorting:
- A vector processor implemented in Chisel☆21Updated 10 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- ☆12Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆20Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆29Updated last month
- Chisel Things for OFDM☆32Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 10 months ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 7 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Fluid Pipelines☆11Updated 7 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 10 months ago
- ☆21Updated 4 years ago
- SoCRocket - Core Repository☆37Updated 8 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 8 years ago
- Chisel implementation of AES☆23Updated 5 years ago