riscv-boom / fpga-zynq
Support for Rocket Chip on Zynq FPGAs
☆40Updated 5 years ago
Alternatives and similar repositories for fpga-zynq:
Users that are interested in fpga-zynq are comparing it to the libraries listed below
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- Chisel Learning Journey☆108Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆63Updated 9 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆35Updated 5 years ago
- QEMU libsystemctlm-soc co-simulation demos.☆144Updated 10 months ago
- Comment on the rocket-chip source code☆178Updated 6 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆102Updated 2 weeks ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- ☆79Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆97Updated last year
- ☆86Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆132Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- ☆170Updated last year
- SystemC/TLM-2.0 Co-simulation framework☆242Updated 5 months ago
- Public release☆50Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆173Updated 8 months ago