lowRISC / fpga-zynqLinks
☆11Updated 10 years ago
Alternatives and similar repositories for fpga-zynq
Users that are interested in fpga-zynq are comparing it to the libraries listed below
Sorting:
- Yet Another RISC-V Implementation☆99Updated last year
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- A 32-bit RISC-V processor for mriscv project☆60Updated 8 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Mini RISC-V SOC☆12Updated 10 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆129Updated 6 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆106Updated 7 years ago
- ☆110Updated 7 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- ☆51Updated last month
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- Platform Level Interrupt Controller☆44Updated last year
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 6 years ago
- A simple RISC-V core, described with Verilog☆27Updated 12 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- The OpenRISC 1000 architectural simulator☆77Updated 9 months ago
- RISC-V RV32IMAFC Core for MCU☆42Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆32Updated 10 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 9 years ago
- ☆40Updated 2 years ago
- AIA IP compliant with the RISC-V AIA spec☆46Updated last year
- LatticeMico32 soft processor☆107Updated 11 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago