Intensivate / learning-journeyLinks
Chisel Learning Journey
☆111Updated 2 years ago
Alternatives and similar repositories for learning-journey
Users that are interested in learning-journey are comparing it to the libraries listed below
Sorting:
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- A dynamic verification library for Chisel.☆159Updated last year
- ☆82Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Chisel components for FPGA projects☆128Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- RISC-V Torture Test☆206Updated last year
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ☆192Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆114Updated 2 months ago
- Provides various testers for chisel users☆100Updated 3 years ago
- Chisel examples and code snippets☆265Updated 3 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆76Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆223Updated 2 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- A Library of Chisel3 Tools for Digital Signal Processing☆242Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- Verilog Configurable Cache☆189Updated last week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated last year
- chipyard in mill :P☆77Updated 2 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- Labs to learn SpinalHDL☆151Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- A basic SpinalHDL project☆88Updated 4 months ago
- Advanced Architecture Labs with CVA6☆72Updated last year